Misalignment of Sampling Clock
The sampling clock is the time base of RFDC time domain. Data passes through each digital function block in parallel or sequential based on the sample clock edge. In addition to this, the analog_sysref signal is re-sampled by the sampling clock. All of these sampling needs impact MTS performance. As there are so many aspects of the RFDC impacted by sampling clock misalignment and the interactions between them, it's difficult to evaluate the exact misalignment caused by sample clock mismatch. However, as a continuous clock, the maximum misalignment of sample clocks is no more than ±T1/2 in the RF digital system.
With exception to the above, the misalignment on converter sampling clock also generates offsets in sampling, and this error won't be identified and corrected by MTS because it's outside of the MTS loop. As a result of this, the user must be careful when undertaking both measurements and design. The following figure illustrates the sampling misalignment.
Align the sampling clocks for the best possible synchronization in a system.
Misalignment due to On-chip RF PLLs
Each tile in RFSoC has the option to use its own RF PLL to generate the RF converter sampling clock on-chip. These on-chip RF PLLs help to avoid high frequency sample clocks routing on board. When enabled, MTS will align the output divider (divider after VCO in a PLL) of each on-chip PLL at the rising edge of analog_sysref, hence align the sample clocks. From the PLL theory, we know the output phase keeps constant relationship with its reference. To keep the sample clock well aligned, the input reference clocks to each pll must be aligned to each other.
Even if the output divider of the RF PLLs will be well aligned by MTS, the VCOs may run at small different phases in the different device samples, voltage and temperature environment. The effect is expected to be small compared to a full period of sampling clock but need to be considered when high accuracy alignment is required.
In third generation of Zynq UltraScale+ RFSoC, the new on-chip clock forwarding feature can distribute the sampling clock from an external synthesizer or from one On-chip RF PLL output to a set of tiles. This can eliminate the misalignment of either multiple external synthesizers or multiple internal PLLs across tiles in a single device and can simplify the clock distribution PCB layout.
For multiple chips alignment, it is required to well align the sampling clocks for each targeted chip and clock distribution feature to minimize this misalignment.
Misalignment due to External Clock Generator
A clock generator has skews between each of its clock outputs typically. The misalignment caused by clock generators can not be identified or corrected by MTS process in general which should be calibrated by the clock generator itself or at system level. For example, the output skew between two clock outputs is ±30ps, and the two output frequencies are 250MHz (T1=4ns). This will generate a phase misalignment around ±2.7degree.
In system design, the clock to each chip may be from the same clock generator, clock buffer or directly distributed from clock amplifier. In any case, the review of the clock paths skew is required to achieve high accuracy alignment in the whole system.