In this source synchronous design, the capture clock is the same as the transmit clock, which is looped back from the TX to the RX core. The transmit clock is forwarded with the data by the TX core. The clock-to-data relation in this design is edge aligned and is shown in the following figure. The XPLL in the RX core needs a PLL input clock apart from the capture clock received with the data. This PLL input clock acts as the input to the XPLL (CLKIN port of the XPLL) and should only be received on a GC/XCC pin. Because this is a multi-bank design (three banks), the wizard instantiates three instances of the XPLLs for each bank. Consequently, the PLL input clock received on the GC/XCC pin is fed to the CLKIN ports of all the XPLL instantiations in the design. The capture clock is received on NIBBLESLICE[0] and NIBBLESLICE[1] of NIBBLE[2], which forwards it to other nibbles through inter-byte and inter-nibble clocking. NIBBLESLICE[0] and NIBBLESLICE[1] have clock forwarding abilities. See the "Inter-nibble and Inter-byte Clocking Within an XPIO Bank" figure in the Versal ACAP SelectIO Resources Architecture Manual (AM010).
The data received at the RX core interface is transmitted to the programmable logic via the PHY and the bank instances, where it gets checked by the PRBS checker.
