In the reference design, the TX core sends out the strobe or the transmit clock
along with the data. The data in this design is generated using the PRBS generator and
the strobe is generated by feeding the pattern 01010101
to the NIBBLESLICEs forwarding the strobe. The data generated by the PRBS generator is
fed into the TX core from the programmable logic, which follows the TX datapath through
a serializer and output delay. The serializer supports 8:1, 4:1, and 2:1 serialization.
This design uses 8:1 serialization. The data is transmitted through the TX data pins of
the core. To understand the data flow operation inside the TX core, see the
Versal ACAP SelectIO Resources Architecture Manual (AM010).
The TX core needs a PLL input clock that acts as the input to the XPLL (CLKIN port of the XPLL) and should only be received on the GC/XCC pin as in the RX core. This option is available if the clock capable (XCC) pin is selected for the XPLL clock source. The PLL input clock is received on the bank0_pll_clkin, bank1_pll_clkin, and bank2_pll_clkin ports of the TX core, which is passed to the XPLLs instantiated in the core for all three banks. The strobe should be transmitted on NIBBLESLICE[0] and NIBBLESLICE[1] to forward it to the RX core.
The PLL input clock to the TX core is fed to the XPLL through a
bank<0/1/2>_pll_clkin port within each bank. In this design, the PLL input clock
is provided similarly to the RX core, except that it is passed through an IBUFDS, and
the single-ended clock is provided to the respective bank<0/1/2>_pll_clkin ports.
The transmit clock can be forwarded either through the data pins or clock forwarding
pins on the TX core. In both cases, a clock pattern of 01010101
needs to be fed to either the data pins or the clock forwarding
pins. This results in the same output clock. The design uses the data pins to forward
the transmit clock. The transmit clock is transmitted on NIBBLESLICE[0] and
NIBBLESLICE[1] to the RX core.