Generating a RX Core

XPHY I/O Source Synchronous Interfaces (XAPP1350)

Document ID
XAPP1350
Release Date
2021-02-04
Revision
1.0 English

After following the previous steps to generate the top-level design, the next step is to generate a TX and RX core for operation. Follow these steps to generate the RX core using the AIOW. See the figures in this section for reference.

  1. To start generating a core for RX, open the IP catalog and search for Advanced I/O Wizard. Double-click Advanced I/O Wizard from the catalog to open the Customize IP window.
  2. For Component Name, enter RX_Ssync_Intrfce_MB, which is used in the reference design.
    Note: The component name should match the module name used in the top-level design.
  3. Under the Basic Tab, set Application to SOURCE SYNCHRONOUS from the drop-down list. Set Bus Direction to RX ONLY.
  4. On the same tab, set the following:
    1. Interface Speed: 1800 Mb/s.
    2. Clock Data Relation: Edge DDR.
    3. PLL Clock Source: Clock Capable Pin.
    4. PLL Input Clock Frequency: 225.
    5. RX Serialization Factor: 8.
    6. The remaining options can be set to the default.
    Figure 1. Multi-Bank RX AIOW Basic Configuration
  5. In the Advanced tab, set the following:
    1. Select REDUCE CONTROL SIGNALS, Enable BLI logic, and Enable DESKEW Logic. When the BLI logic is enabled, the BLI registers between the fabric and the XPHY can be used to help with timing closure. When deskew logic is enabled, the instantiated XPLLs are deskew enabled.

      When Deskew Logic is enabled, XPLLs instantiated will be deskew enabled.

    2. Differential I/O Std: LVDS15.
    3. Number of Banks: 3 (because this is a multi-bank design).
    Figure 2. Multi-Bank RX AIOW Advanced Configuration
  6. In the Pin Configuration tab, make four entries in the table. One entry is for the data and the strobe per bank and the other is for the common PLL input clock for all the banks.
    • Data and the Strobe Setting #1
      • Pin Direction = RX
      • I/O Type = Differential
      • Signal Type = Data
      • Strobe I/O Type = Differential
      • Strobe Name = strobe_b0
      • Signal Name = Rx_data_b0
      • Number of Data Channels = 25
    • Data and the Strobe Setting #2
      • Pin Direction = RX
      • I/O Type = Differential
      • Signal Type = Data
      • Strobe I/O Type = Differential
      • Strobe Name = strobe_b1
      • Signal Name = Rx_data_b1
      • Number of Data Channels = 25
    • Data and the Strobe Setting #3
      • Pin Direction = RX
      • I/O Type = Differential
      • Signal Type = Data
      • Strobe I/O Type = Differential
      • Strobe Name = strobe_b2
      • Signal Name = Rx_data_b2
      • Number of Data Channels = 25
    • PLL Input Clock Setting
      • Pin Direction = RX
      • I/O Type = Differential
      • Signal Type = Input Clock
      • Signal Name = clk
      • Number of Data Channels = 1
    Figure 3. Multi-Bank RX AIOW Pin Configuration
  7. Check the Summary tab. It should show 158 RX pins enabled (25 pairs of data x 3 banks + 1 pair of capture clocks x 3 banks + a pair for the PLL input clock).
    Note: In the following figure, the number of strobe pins enabled is incorrect. The correct value is 6.
    Figure 4. Multi-Bank RX AIOW Summary
  8. Click OK after reviewing the settings. The IP is now customized and the Generate the Output Products prompt appears. Set the Synthesis Option to Out of context per IP and then click Generate to launch the design run for the newly generated RX core. See the following table.
Table 1. Receiver Requirements Multi-Bank
  Requirement
Component name RX_Ssync_Intrfce_MB
Bus direction RX_ONLY
Serialization factor 8
Interface speed (Mb/s) 1800 Mb/s
Clock data relation Edge DDR
PLL clock source Clock capable pin
PLL input clock frequency 225 MHz
Include PLL in core Yes
PLL CLKOUT1 No
FIFO WRCLK OUT No
Reduce control signals Yes
Enable delay control signals No
Enable BLI logic Yes
Enable deskew logic Yes
Differential I/O Std LVDS15
Number of banks 3
Pin configuration As mentioned above. The configuration occupies 158 pins across all three banks.