Generating a TX Core

Follow these steps to generate the TX core using the AIOW. See the figures in this section for reference.

1. To start generating a core for TX, open the IP catalog and search for Advanced I/O Wizard. Double-click Advanced I/O Wizard to open the Customize IP window for the wizard.
2. For Component Name, enter TX_Ssync_Intrfce_MB, which is used in the reference design.
   Note: The component name should match the module name used in the top-level design.
3. Under the Basic Tab, set Application to SOURCE SYNCHRONOUS from the drop-down list, and set Bus Direction to TX ONLY.
4. On the same tab, set the following:
   1. Interface Speed: 1800 Mb/s.
   2. Clock Data Relation: Edge DDR.
   3. PLL Clock Source: Fabric (Driven by BUFG).
   4. PLL Input Clock Frequency: 225.
   5. Forwarded Clock Phase to 0.
   6. TX Serialization Factor: 8.
   7. The remaining options can be set to the default.
   Figure 1. Multi-Bank RX AIOW Basic Configuration
5. In the Advanced tab, set the following:
   1. PLL CLKOUT1: 225
   2. Select REDUCE CONTROL SIGNALS, Enable BLI logic, and Enable DESKEW Logic. When the BLI logic is enabled, the BLI registers between the fabric and the XPHY can be used to help with timing closure. When the deskew logic is enabled, the instantiated XPLLs are deskew enabled.
   3. Differential I/O Std: LVDS15
   4. Number of Banks: 3 (because this is a multi-bank design).
   Figure 2. Multi-Bank RX AIOW Advanced Configuration
   
6. In the Pin Configuration tab, add three entries in the table. This entry is for the data with I/O type as differential, signal type as data, and mark the signal name as “Tx_data_b#”, where # is the bank number. This also accounts for the transmit clock.
   • Data Setting #1
     • Pin Direction = TX
     • I/O Type = Differential
     • Signal Type = Data
     • Signal Name = Tx_data_b0
     • Number of Data Channels = 26
   • Data Setting #2
     • Pin Direction = TX
     • I/O Type = Differential
     • Signal Type = Data
     • Signal Name = Tx_data_b1
     • Number of Data Channels = 26
   • Data Setting #3
     • Pin Direction = TX
     • I/O Type = Differential
     • Signal Type = Data
     • Signal Name = Tx_data_b2
     • Number of Data Channels = 26
   Figure 3. Multi-Bank RX AIOW Pin Configuration
7. Check the Summary tab. It should show 156 TX pins enabled (25 pairs of data x 3 banks + 1 pair of transmit clock x 3 banks).
   Figure 4. Multi-Bank RX AIOW Summary
8. Click OK after reviewing the settings. The IP is now customized and the Generate the Output Products prompt appears. Set the Synthesis Option to Out of context per IP and then click Generate to launch the design run for the newly generated TX core.