Introduction

XPHY I/O Source Synchronous Interfaces (XAPP1350)

Document ID
XAPP1350
Release Date
2021-02-04
Revision
1.0 English

This application note covers two designs for a source synchronous application using the AIOW:

  • Single-bank source synchronous design
  • Multi-bank source synchronous design

The AIOW provides the option to choose the number of banks, but not to exceed three banks. The wizard creates one bank instance for each bank. Both designs use low-voltage differential signaling (LVDS) for data transmission speeds at 1800 Mb/s. See the Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957) for the speeds supported that can transmit and receive the LVDS standard. The underlying I/O and XPLL clocking architecture for these designs can be found in the Versal ACAP SelectIO Resources Architecture Manual (AM010) and Versal ACAP Clocking Resources Architecture Manual (AM003), respectively.