Pre-Core Generation Setup

Before following the procedure in this section, download the reference design files from the Xilinx website. For detailed information about the design files, see Reference Design.

The following steps describe how to configure and set up the project before building the TX and RX cores using the AIOW.

1. Browse to the folder where the zipped file is downloaded.
2. Unzip the file and open the top-level xapp1350 folder. Check the Multi_Bank_Ssync_Loopback_Design folder, which has all the necessary design files under the Sources, Constraints, and Testbench folders.
3. Create a separate directory named Versal_Ssync_RxTx_Intrfce_MB to build the new project.
4. Launch the Vivado tools 2020.1 or later from the newly created directory.
5. Under Quick Start , select Create Project.
6. Click Next for the prompt to Create a New Vivado Project and use Versal_Ssync_RxTx_Intrfce_MB for the name of the project. Deselect Create a project subdirectory.
7. Click Next. For Project Type, select RTL project. Deselect Do not specify sources at this time.
8. The next step is to add the sources. Add the source files from the Sources folder under the Multi_Bank_Ssync_Loopback_Design folder.
9. Add the files toplevel_mb.sv, Prbs_Any.vhd, Prbs_RxTx.vhd, and sync_cell.sv. Make sure the Library is set to xil_defaultlib and the files are used for synthesis and simulation by setting it under HDL Source For.
10. Similarly, add the file toplevel_testbench_mb.sv from the Testbench folder under the Multi_Bank_Ssync_Loopback_Design folder. Make sure the Library is set to xil_defaultlib and the file is used just for simulation by setting it under HDL Source For.
11. Select Scan and add RTL include files into project and Copy sources into project. Set the Target Language to Verilog and the Simulator Language to Mixed.
12. Click Next to proceed to adding the constraint files.
13. Add the files toplevel_mb.xdc and attributes_mb.xdc from the Constraints folder under the Multi_Bank_Ssync_Loopback_Design folder. Select Copy constraints files into project.
14. Click Next to proceed to select the part for the project. Select part xcvc1902-vsva2197-2MP-e-S-eS1 for the reference designs and then click Next.
15. On the summary page for the project, make sure all the details match the settings and then click Finish.
16. The Vivado tools should create a project and display the hierarchy of the files under the Sources folder.
17. Under the Sources folder, right-click on attributes_mb.xdc and click Source File Properties. Under Source File Properties, open the tab for Properties and under USED_IN, select opt_design_post.