Simulating the Design

The design is tested with the Vivado Simulator 2020.1. This section describes how to launch the simulation. Assuming the Vivado project is already created for the design, follow these steps to simulate the design.

1. Click Run Simulation under Simulation from the Flow Navigator.
2. From the listed options, select Run Behavioral Simulation, which elaborates the design and launches the simulation.
3. The run time by default is 1 ns for the simulation. It takes about 240 μs for the intf_rdy to be asserted for the RX core. Only after its assertion and the next Prbs_Valid, should the data be compared. Consequently, launch the simulation for a duration of more than 240 μs using the box highlighted in the following figure. A waveform config file toplevel_testbench_behav.wcfg is provided under the Testbench directory to add a list of signals for the simulation.
   Figure 1. Multi-Bank Design - Changing the Simulation Time
4. Once the behavioral simulation is finished, check for any errors by observing error flags for the PRBS generator and checker. For example, int_prbs_b<0/1/2>_err<num> reports the errors for each instantiation of the PRBS generator and checker. Int_prbs_b0_err24 denotes the error flag for the PRBS module instantiated for NIBBLE[2], NIBBLESLICE[4] of bank instance 0. Int_prbs_err_b<0/1/2>_00 denotes the error for any NIBBLESLICEs on NIBBLE[0]. Int_prbs_err_b<0/1/2>_12 denotes the error for any NIBBLESLICEs on NIBBLE[1] and NIBBLE[2]. Int_prbs_err_b0_all denotes an error on any NIBBLESLICE across all the nibbles in bank instance 0. Int_prbs_err_all denotes an error on any NIBBLESLICE across all the nibbles in any of the bank instances.