The design uses the toplevel_testbench_mb.sv file to create a simple test bench. This test bench connects the TX core to the RX core via loopback<num>_b<0/1/2> connections (wires). The transmit clock is transmitted on loopback13_b<0/1/2> and loopback14_b<0/1/2> loopback wires. All the other loopback connections are used to transmit and receive the data. The clock-to-data relationship is edge aligned as shown in the following figure captured from the simulation.
The test bench provides the necessary clock and resets to the design and triggers its operation. The PLL input clock is provided at 4.444 ns (225 MHz) to the RX and TX cores. The transmit/capture clock toggles at 900 Mb/s (1.111 ns period) as shown in the following figure. Because the system is double data rate, the interface operates at 1800 Mb/s.
The Vivado 2020.1 tools allow only behavioral simulation when using the AIOW.