In the single-bank source synchronous reference design, all nine XPHY nibbles of the XPIO bank are used. Each XPHY nibble contains six XPHY NIBBLESLICEs that can transmit and receive data from six individual I/O pins, for a total of 54 pins/bank. The transmit clock can be forwarded from the transmit core either by the clock forward pins or by the transmit data pins from the bank. In this design, the transmit clock is forwarded by the clock forward pins. Because the design uses the LVDS standard for the I/Os, data and clock are available in pairs of I/O pins.
The wizard configures clocking circuitry using an XPLL that is needed to support these configurations. In this design, the XPLL is instantiated in the core and the wizard is used to configure the XPLL clock frequency. The XPLL input clock is fed through a global clock (GC) input pin. The core uses one differential pair of I/O as the PLL input clock for RX/TX, one differential pair of I/O for the transmit/capture clock, and the rest for the data. Consequently, the Transmit and Receive core has 25 pairs for data transmission and reception. See the Advanced I/O Wizard LogiCORE IP Product Guide (PG320) to understand how to use the wizard beyond the scope of this application note.
The reference design uses the PRBS generator and checker to exercise the I/Os.
The design files for the PRBS generator and checker are provided in the design suite.
The generator and checker are instantiated in the top-level source files. The PRBS
generator generates the data and feeds the TX core, which serializes it and transmits it
to the RX core via an external loopback in the test bench. The RX core feeds the data to
the PRBS checker after deserializing it. Because the design is a simulation-only design,
the external loopback is achieved via wires in the test bench. The checker flags an
error if it detects any mismatch. The block diagram of the reference design is shown in
the following figure. The transmit clock is generated by feeding a 01010101 pattern to the corresponding clock forwarding
pins.
