Top-Level using TX and RX Advanced I/O Wizard Cores

XPHY I/O Source Synchronous Interfaces (XAPP1350)

Document ID
XAPP1350
Release Date
2021-02-04
Revision
1.0 English

The top-level design file (toplevel_mb.sv) includes the toplevel_mb module. This module helps connect the interfaces such as clocks, debug ports, I/O ports, etc., with the appropriate sources. The top-level design houses the instantiation of both the RX and the TX cores. To test the design, the PRBS patterns from the custom PRBS generator provided in the design suite can be used to generate and check the received data.

The PRBS generator generates the 8-bit data for each pair and feeds it to the TX core, which in turn transmits it through the TX pins. The PRBS generator also houses an error injecting mechanism. The data is received on the I/O ports of the RX core through external loopback. The RX core forwards the deserialized data through the PHY to the programmable logic. This deserialized data is then fed into the PRBS checker to check for any failures.

The top-level design files include two constraints files. The toplevel_mb.xdc file is used to create clocks for the design and assign a location to all the I/O ports in the design. The attributes_mb.xdc file is provided as a placeholder for any attributes to be added for non-default bank instances. The current design is provided as an empty file because it does not have any constraints for non-default bank instances. This file must be marked for post-opt usage. The current release of the Vivado tools fails to recognize any bank instances before the optimization stage, and consequently, the design uses two separate constraints files. As a result, any constraints to modify the attributes of the non-default bank instance are recognized, but the ones for the non-default bank instances are ignored. Consequently, the second constraint file needs to be added and marked to be used for post-optimization.

To set the Xilinx design constraints (XDC) to be used in post_opt, open the Vivado tools and follow these steps.

  1. Select the XDC file, right-click, and click Source File Properties.
  2. Select Properties from the Source File Properties window.
  3. Navigate to USED IN. Move opt_design_post from left to right and synthesis and implementation from right to left as shown in the following figure.
    Figure 1. Setting the XDC to be Used in Post_Opt
  4. Click OK.

The reference design constrains the design to optimally support high data rates. This file is used to create clocks for the design, assign locations or pins to all the I/O ports in the design, and set attributes if needed. The reference design constrains the design to optimally support high data rates. The user must constrain the TX and RX ports. The Vivado tools can assign the XPHY nibbles to the XPHY sites.

In the reference design, bank 706, bank 707, and bank 708 for part xcvc1902-vsva2197-2MP-e-S-eS1 are used for the TX core and bank 703, bank 704, and bank 705 are used for the RX core. The RX core has one pair reserved for the PLL input clock per bank, the design assigns IO_L9P_GC_XCC_N3P0_M1P72_704_BE31 and IO_L9N_GC_XCC_N3P1_M1P73_704_BD32 in the constraint file for bank 704. Similarly, IO_L6P_GC_XCC_N2P0_M1P66_704_BC31 and IO_L6N_GC_XCC_N2P1_M1P67_704_BC30 are assigned to the capture clock. The corresponding pins in other banks for both the TX core and RX core are assigned similarly.

At this point all the files are added to the project and both the RX and TX cores are generated. The design is ready to be synthesized and implemented.