This TX core is set up for a data rate of 1800 Mb/s. Also, the core is configured and tested for LVDS15 in this reference design. The PLL input clock to the TX core is fed to the XPLL through a bank<0/1/2>_pll_clkin port within each bank. In the design, the PLL input clock is provided similarly to the RX core, except that it is passed through an IBUFDS, and the single-ended clock is provided to the respective bank<0/1/2>_pll_clkin ports. An XPIO bank has 54 pins and the design uses 52 pins in the form of 25 pairs of data pins and one pair of strobe for each of the three bank instances. The RX core has a pair of pins reserved for the PLL input clock, and consequently, the TX core leaves an equivalent pair unused. The design constrains the ports for the transmit interfaces and the wizard takes care of the placement.