MATLAB® scripts are used to generate random test vectors as inputs and corresponding reference outputs. The completed AI Engine design is validated against the MATLAB reference model to confirm the correct behavior. For the DDC design, there are 32 output AXI streams for 32 antennas. A make file script is included in the reference design to compare all the outputs of the AI Engine SystemC simulation results with the golden test vectors generated by MATLAB. Figure 1 (a) and Figure 2 (a) show the bit-accurate comparison of the SystemC simulation and the reference MATLAB model of the example design, where the outputs bit-true match those of the reference model.
The time stamps in the Versal SystemC Simulation (ESS) output can be used to measure the time duration from the first output sample to the last. Also because the number of output samples can be counted in the output file too, an estimate of throughput can be computed; that is, the throughput can be calculated by dividing the total number of outputs by the time interval between first sample and the last sample. The reference design comes with a Makefile that measures the throughput. As shown in Figure 1 (b) and Figure 2 (b), the ESS simulation of the AI Engine DDC design indicates that the DDC design throughput is about 207 MSPS for the 5c LTE case, much higher than the nominal sample rate of five LTE carriers at 153.6 MSPS. The throughput for the 5G NR configuration is about 180 MSPS, much higher than the nominal sample rate of 122.88 MSPS. There is sufficient margin in the DDC design based on the computed throughput.
When the AI Engine DDC module passes ESS simulation validation, it is ready for integration in a complete system that consists of programmable logic, processor sub-system, memory controller, and other blocks in Versal AI Core devices.