Implementation Result

Digital Down-conversion Chain Implementation on AI Engine (XAPP1351)

Document ID
XAPP1351
Release Date
2021-02-15
Revision
1.0 English

The DDC kernels of this application note are profiled and the results are listed in the following table. The actual utilization is measured by:

Table 1. DDC Kernel Profile
Kernel Name Interface Format Function Counts Utilization Lower Boundary Actual Utilization Implementation Loss
FIR199

Nature in

Nature out

1705 cycles 76.9% 81.9% 5%
FIR89

Nature in

Nature out

238 cycles 9.3% 11.5% 2.2%
HBF47_2D

Interleaved in

Nature out

266 cycles 12.3% 12.8% 0.5%
HBF23_2D

Nature in

Nature out

65 cycles 1.6% 3.2% 1.6%
HBF11_2D

Interleaved in

Nature out

54 cycles 1.6% 2.6% 1%
Mixer

Nature in

Interleaved out

571 cycles 23% 27.5% 4.5%

The profiling results show a small implementation loss compared to the utilization lower bound.

The data flow and interconnects among the AI Engines are described in a graph file and the compilation result of a 32-antenna DDC design is shown in the following figure. Bubbles with same color are mapped and executed in the same AI Engine. The light gray boxes are DMAs and buffers automatically generated by the Xilinx tools depending on the data flow specified by the user.

Figure 1. Compilation Result of a 1 out of 32 Antenna DDC Design