Graph Design Details

The dataflow of an AI Engine design is defined by a C++ class referred to as the graph design. In the beamforming reference design, one cascading chain is defined in the subgraph bfCascadingChain. The template parameters xoff and yoff define the coordinate of the leftmost AI Engine and len specifies the length of the cascading chain in terms of the number of AI Engines. Because every AI Engine needs two inputs for data and coefficients, respectively, the whole chain has two len inputs and only one output.

template <int xoff, int yoff, int len>
class bfCascadeChain: public graph {
private:
 kernel core[len];
public:
 port<input> din[len];
 port<input> cin[len];
 port<output> out;
 bfCascadeChain() { 
 ... 
 } ; 
}; // end of class bfCascadeChain

With this subgraph, beamforming designs can be constructed by instantiating several cascading chains of certain lengths. For a 5G NR 100 MHz system with 64 antennas and 32 layers, downlink beamforming can be described as eight cascading chains of length 4, and uplink as four chains of length 8. Some example graph C++ code is shown in the following table.

//-------------------------------------
// DL 64 Antenna 32 Layer
//-------------------------------------
template <int xoff, int yoff> 
class DL64A32L: public graph {
private:
bfCascadeChain<xoff, yoff+0, 4> bf0;
 bfCascadeChain<xoff, yoff+1, 4> bf1;
 bfCascadeChain<xoff, yoff+2, 4> bf2;
 bfCascadeChain<xoff, yoff+3, 4> bf3;
 bfCascadeChain<xoff+4, yoff+0, 4> bf4;
 bfCascadeChain<xoff+4, yoff+1, 4> bf5;
 bfCascadeChain<xoff+4, yoff+2, 4> bf6;
 bfCascadeChain<xoff+4, yoff+3, 4> bf7;
public:
 port<input> din[4];
 port<input> cin[32];
 port<output> out[8];
 DL64A32L(){
 ...
 };
}; // end of DL64A32L

//-------------------------------------
//  UL 64 Antenna 32 Layer
//-------------------------------------
template <int xoff, int yoff> 
class UL64A32L: public graph {
private:
  bfCascadeChain<xoff, yoff+0, 8> bf0;
  bfCascadeChain<xoff, yoff+1, 8> bf1;
  bfCascadeChain<xoff, yoff+2, 8> bf2;
  bfCascadeChain<xoff, yoff+3, 8> bf3;




public:
  port<input> din[8];
  port<input> cin[32];
  port<output> out[4];
  
  UL64A32L(){
 		...
  }; 
};  // end of UL64A32L

Xilinx tools compile the graph design and automatically generate block diagrams to represent the compilation result. The following two figures show one example using the 64-antenna 32-layer 100 MHz beamforming reference design. Every colored bubble represents one AI Engine, and gray boxes are DMAs and memories used by the design. Xilinx tools automatically configure the DMAs, AXI switches, and PL-AI Engine interfaces for the graph design.