AXI SmartConnect

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

Document ID
XAPP1353
Release Date
2022-05-04
Revision
1.1 English

The XMPU_PL functionality relies on access to the AXI MasterID contained in transactions from PS masters. The S_AXI and S_AXI_XMPU have been implemented as AXI4 full interfaces to maintain the AxUser port connections which carries the MasterID values. If an inter-connect block is needed between the PS and the XMPU_PL, use the AXI SmartConnect, as shown in the following figure, instead of AXI Interconnect. AXI Interconnect blocks to do not pass the AxUser bus and block the transmission of the MasterIDs. However, AXI Interconnect blocks may be used to connect to PL Masters or multiple end-point slaves, as MasterIDs are not utilized in those connections.

Figure 1. Using AXI SmartConnect