Appendix A: Master ID List

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

Document ID
XAPP1353
Release Date
2022-05-04
Revision
1.1 English
Table 1. PS Master IDs
Master ID Mask   Master ID Mask
MID_RPU0 x"0000" x"03F0" MID_GPU x"00C4" x"03FF"
MID_RPU1 x"0010" x"03F0" MID_DAP_AXI x"00C5" x"03FF"
MID_PMU x"0040" x"03FF" MID_PCIE x"00D0" x"03FF"
MID_USB0 x"0060" x"03FF" MID_DP_DMA0 x"00E0" x"03FE"
MID_USB1 x"0061" x"03FF" MID_DP_DMA1 x"00E1" x"03FE"
MID_DAP_APB x"0062" x"03FF" MID_DP_DMA2 x"00E2" x"03FE"
MID_LPD_DMA0 x"0068" x"03FE" MID_DP_DMA3 x"00E3" x"03FE"
MID_LPD_DMA1 x"0069" x"03FE" MID_DP_DMA4 x"00E4" x"03FE"
MID_LPD_DMA2 x"006A" x"03FE" MID_DP_DMA5 x"00E5" x"03FE"
MID_LPD_DMA2 x"03FB" x"03FE" MID_FPD_DMA0 x"00E8" x"03FE"
MID_LPD_DMA4 x"006C" x"03FE" MID_FPD_DMA1 x"00E9" x"03FE"
MID_LPD_DMA5 x"006D" x"03FE" MID_FPD_DMA2 x"00EA" x"03FE"
MID_LPD_DMA6 x"006E" x"03FE" MID_FPD_DMA3 x"00EB" x"03FE"
MID_LPD_DMA7 x"006F" x"03FE" MID_FPD_DMA4 x"00EC" x"03FE"
MID_SD0 x"0070" x"03FF" MID_FPD_DMA5 x"00ED" x"03FE"
MID_SD1 x"0071" x"03FF" MID_FPD_DMA6 x"00EE" x"03FE"
MID_NAND x"0072" x"03FF" MID_FPD_DMA7 x"00EF" x"03FE"
MID_QSPI x"0073" x"03FF" MID_HPC0_FPD x"0200" x"03C0"
MID_GEM0 x"0074" x"03FF" MID_HPC1_FPD x"0240" x"03C0"
MID_GEM1 x"0075" x"03FF" MID_HP0_FPD x"0280" x"03C0"
MID_GEM2 x"0076" x"03FF" MID_HP1_FPD x"02C0" x"03C0"
MID_GEM3 x"0077" x"03FF" MID_HP2_FPD x"0300" x"03C0"
MID_APU x"0080" x"03FF" MID_HP3_LPD x"0340" x"03C0"
MID_APU x"00C0" x"03C0" MID_PL_LPD x"0380" x"03C0"
MID_SATA1 x"00C1" x"03FF" MID_ACE_FPD x"03C0" x"03C0"