CTRL Control Register

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

Document ID
XAPP1353
Release Date
2022-05-04
Revision
1.1 English

The CTRL register is shown in the following table.

Table 1. XMPU_PL CTRL Register Bit Field Summary
Field Name Bits Type Reset Value Description
Reserved 31:7 ro 0x0 Reserved
PoisonAxiResp 6:5 rw 0x3

Select AXI response to poisoned transactions.

  • 0x0: OKAY
  • 0x0: EXOKAY
  • 0x2: SLVERR
  • x3: DECERR
Note: If ExternalSinkEn is enabled, then the peripheral at the address specified in the POISON register transmits the response.
ExternalSinkEn 4 rw 0x0

0: Transactions poisoned by address terminate in the XMPU_PL

1: Transactions poisoned by address are routed to a sink specified by POISON[PL_SINK_ADDR]

PoisonAttributeEn 3 rw 0x1

0: Transaction is not poisoned. AxProt[1] remains at original value.

1: Enables Poison by Address. Transaction routed to internal or external sink address. See CTRL[ExternalSinkEn]

PoisonAddressEn 2 rw 0x1

0: Transaction is not poisoned. Transaction proceeds to original address.

1: Enables Poison by Address. Transaction routed to internal or external sink address. See CTRL[ExternalSinkEn]

DefWrAllowed 0 rw 0x1

Default Write Allowed. Ensure the following steps are implemented if a write transaction address and master ID miss in the Region List:

0: poison the transaction with a Write Permission Violation

1: transaction allowed, regardless of security level

DefRdAllowed 0 rw 0x1

Default Read Allowed. If a read transaction address and master ID miss in the Region List, then:

0: poison the transaction with a Read Permission Violation

1: transaction allowed, regardless of security level