Handling XMPU_PL Interrupts in the PMU (EM) Error Manager

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

Document ID
XAPP1353
Release Date
2022-05-04
Revision
v1.1 English

In the PL design shown in Figure 21, the zupl_xmpu reference core interrupt output port, irq, is routed to the PS ports pl_ps_irq[0] and pmu_error_from_pl[0]. The pl_ps_irq signal can be used by the global interrupt controller (GIC) to trigger interrupts in the RPU and APU processors. Similarly, the pmu_error_from_pl signal triggers an interrupt in the PMU Error Manager.

The PMU Error Manager is customized to respond to system events. The default configuration of the EmEventHandler, in xpfw_mod_em.c, installs event detection modules for the PMU global registers ERROR_STATUS_1 and ERROR_STATUS_2. The ERROR_STATUS_2 register provides event triggers for pmu_error_from_pl [0:3] on bits ERROR_STATUS_2[2:5]. Refer to Zynq UltraScale+ Device Register Reference (UG1087) for more details of the PMU global registers.

The Zynq UltraScale+ MPSoC: Software Developers Guide (UG1137) provides a detailed description of the PMU firmware and error manager. To enable an event handler for the PL signals, an XPfw_EmSetAction function call is added to the EmCfgInit function in xpfw_mod_em.c, shown in the following figure.

Figure 1. Error Manager Configuration Initialization in xpfw_mod_em.c

The EM error IDs are defined in xpfw_error_manager.h. EM_ERR_ID_PL (8U) identifies the PL to PS portion of the ERROR_STATUS_2 register. The XPfw_EmSetAction function call provides the error ID, action type and event handler. Setting the action type to EM_ACTION_CUSTOM enables a callback to the event handler.

In the following figure, the event handler, PL_ErrorHandler, has been added to xpfw_mod_em.c. This specific example shows the event handler, PL_ErrorHandler, calls for the XMPU_PL interrupt handler, XmpuPl_Interrupt_Handler, and then clears the event in the ERROR_STATUS_2 Register.

Note: Only PL_TO_PS events are cleared by this handler.
Figure 2. PL Event Handler

The XmpuPl_Interrupt_Handler function is shown in the following figure:

Figure 3. XMPU_PL Interrupt Handler

The XmpuPl_Interrupt_Handler function has been specifically designed for the purposes of this demonstration to output XMPU_PL violations in the same format as that used for the XMPU/XPPU (PS) events handled in xpfw_xpu. For reference, see figure 49 and figure 53.

As with any handler written for XMPU_PL interrupts, you must first get the interrupt status from the ISR register to determine the violation type (read or write). The ERR_STATUS1 and ERR_STATUS2 registers provide the originating AXI address and Master ID, respectively. After printing out the violation data, the interrupt status is cleared from the ISR register. To identify the PS master from the master ID, the static XpuMasterID list has been copied from xpfw_xpu.c and placed into the xpfw_pl_xmpu.c file.

Note: In the Vitis 2019.2 version of the pmufw imported files, the XpuMasterID struct content has been reduced to the APU and RPU0 entries to conserve memory consumption. These are the only masters utilized in this demonstration.