In the PL design shown in Figure 21, the
zupl_xmpu reference core interrupt output port,
irq, is routed to the PS ports
pl_ps_irq signal can be used by the global
interrupt controller (GIC) to trigger interrupts in the RPU and APU processors.
pmu_error_from_pl signal triggers an
interrupt in the PMU Error Manager.
The PMU Error Manager is customized to respond to system events. The default
configuration of the EmEventHandler, in
installs event detection modules for the PMU global registers ERROR_STATUS_1 and
ERROR_STATUS_2. The ERROR_STATUS_2 register provides event triggers for
pmu_error_from_pl [0:3] on bits ERROR_STATUS_2[2:5]. Refer to
Zynq UltraScale+ Device Register Reference (UG1087) for more details of the PMU
Zynq UltraScale+ MPSoC: Software Developers Guide (UG1137) provides a
detailed description of the PMU firmware and error manager. To enable an event handler
for the PL signals, an XPfw_EmSetAction function call is added to the EmCfgInit function
xpfw_mod_em.c, shown in the following figure.
The EM error IDs are defined in
(8U) identifies the PL to PS portion of the ERROR_STATUS_2 register. The
XPfw_EmSetAction function call provides the error ID, action type and event handler.
Setting the action type to EM_ACTION_CUSTOM enables a callback to the event handler.
In the following figure, the event handler, PL_ErrorHandler, has been added to
xpfw_mod_em.c. This specific example shows the
event handler, PL_ErrorHandler, calls for the XMPU_PL interrupt handler,
XmpuPl_Interrupt_Handler, and then clears the event in the ERROR_STATUS_2 Register.
The XmpuPl_Interrupt_Handler function is shown in the following figure:
The XmpuPl_Interrupt_Handler function has been specifically designed for the
purposes of this demonstration to output XMPU_PL violations in the same format as that
used for the XMPU/XPPU (PS) events handled in
For reference, see figure 49 and figure
As with any handler written for XMPU_PL interrupts, you must first get the
interrupt status from the ISR register to determine the violation type (read or write).
The ERR_STATUS1 and ERR_STATUS2 registers provide the originating AXI address and Master
ID, respectively. After printing out the violation data, the interrupt status is cleared
from the ISR register. To identify the PS master from the master ID, the static
XpuMasterID list has been copied from
placed into the