ISR Interrupt Status Register

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

Document ID
XAPP1353
Release Date
2022-05-04
Revision
1.1 English

The ISR register interrupts are shown in the following table. The bits in the status register are sticky and remain asserted until cleared by writing a 1 to the asserted bit.

Reading AXI Access Violations:

  • 0: no interrupt request
  • 1: interrupt requested

Writing AXI Access Violations:

  • 0: no effect
  • 1: clear bit to 0

If a Status bit is 1 and its Mask is 0, then the IRQ interrupt signal is activated to the interrupt controller. The first AXI violation is recorded. Once an ISR[3:1] status bit is set, subsequent AXI violations are not recorded, but their transactions are poisoned. The status bits are cleared by a system reset and can be cleared by a software

Table 1. ISR (XMPU_PL) Register Bit Field Summary
Field Name Bits Type Reset Value Description
Reserved 31:4 ro 0x0

Reserved

SecurityVIO 3 wtc 0x0

Security violation by AXI Master: A non-secure master tries to access a secure memory space.

WrPermVIO 2 wtc 0x0

Write Permission violation by AXI Master. Write access attempted to enabled region with WrAllowed = 0. Or the transaction missed in the region list and CNTRL [DefWrAllowed] = 0.

RdPermVIO 1 wtc 0x0

Read Permission violation by AXI Master.

Read access attempted to enabled region with RdAllowed = 0.The transaction missed in the region list and CNTRL [DefRdAllowed] = 0.
Reserved 0 ro 0x0 Reserved