Module Registers Summary

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

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v1.1 English

The XMPU_PL module registers and address offsets are shown in the following table. The following sections provide the bit field definitions for each module register.

Table 1. XMPU_PL Module Registers
Register Name Address Offset Type Description
Control and Status
CTRL 0x000 mixed Control and Implementation
ERR_STATUS1 0x004 ro Error Status, Violation Address
ERR_STATUS2 0x008 ro Error Status, Violation Master ID
POISON 0x00C rw External Sink Address
ISR 0x010 mixed Interrupt Status and Clear
IMR 0x014 ro Interrupt Mask
IEN 0x018 wo Interrupt Enable
IDS 0x01C wo Interrupt Disable
LOCK 0x020 rw Register Write Lock
LOCK_BYPASS 0x024 mixed Enable Master Access
REGIONS 0x028 ro Number of Active Regions
Region Control
R{00:15}_START 0x100+ mixed Region starting base address
R{00:15}_END 0x104+ ro Region ending address
R{00:15}_MASTERS 0x108+ ro Select authorized PS Masters
R{00:15}_CONFIG 0x10C+ rw Enable and Configure