BOOT.bin file for the RPU fault
injection application <build_path>/rpu_fault_injection/BOOT.bin to the SD Card, place
the SD Card into the socket J100, and power the board.
The read/write address tests shown in term 1 must either PASS or FAIL in correspondence to the isolation layout of the system. You can refer to Figure 14 for further clarity.
The RPU is designated non-secure, and hence can successfully read/write to NS (non-secure) and NS_SHARED (non-secure shared with secure) memory and peripherals. Each time a test fails, a violation is reported by the PMU in term 0.
Examine the term 0 output for the PL memory and peripheral tests, shown in the previous figure. The failed test, on PL_BRAM_S_BASE, violations are reported in term 1, as shown in the following figure.
ErrorId:8corresponds to activity detected on the pmu_error_from_pl port used by the zupl_xmpu_v1_0 irq port, in the PL design, to communicate interrupts to the PMU. The code to respond to this interrupt type has been added to the PMU firmware.
You can refer to A closer Look at the Platform Management Unit (PMU) for a detailed understanding of how this was accomplished.
As shown in the previous figure, the LOCK register is read and indicates the status as locked. The register is cleared and then re-read. The RPU is an authorized master in the LOCK_BYPASS registers and retains write privileges to the XMPU_PL configuration registers.