Rxx_CONFIG Region Configuration Register

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

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v1.1 English

The R[n]_CONFIG register is shown in the following table. If a transaction address is within an enabled region's start and end addresses, then the [WrAllowed]/[RdAllowed] condition is checked. If the transaction R/W type is allowed, then the security Master ID check is performed. When more than one address region includes the transaction address (regions overlap) or if any region poisons the transaction, then it takes precedence.

Note: Address Offset: 0x00000[n]0C
Table 1. R[n]_CONFIG (XMPU_PL) Register Bit Field Summary
Field Name Bits Type Reset Value Description
Reserved 31:6 ro 0x0 Reserved
MidCheckDisable 5 rw 0x0

0: [default] Master ID is checked. Transactions are only considered secure when MasterID aligns with R00_MASTERS[] Register.

1: Disables Master ID check during security check. Any transaction with AxProt[1] = 0 will be considered Secure.

Note: PL_Masters such as MicroBlazeâ„¢ do not propagate a MasterID. Setting MidCheckDisable = 1 allows WrAllow and RdAllow to define the permissions for the region.
NSCheckType 4 rw 0x0

Non-secure Region Check Type. Secure masters may or may not be allowed to access Non-Secure (NS) memory regions.

0: relaxed checking; secure requests may access a non-secure (NS) region.

1: strict checking; secure requests may only access a secure region.

A non-secure access request can only access non-secure regions regardless of bit setting.

RegionNS 3 rw 0x0

Select security level of region:

0: secure.

1: non-secure (NS).

WrAllowed 2 rw 0x1

Allow writers to region:

0: not allowed; write transaction poisoned.

1: allowed.

RdAllowed 1 rw 0x1

Allow writers to region:

0: not allowed; read transaction poisoned.

1: allowed.

Enable 0 rw 0x0

Enable region:


1: enabled.