The XMPU_PL block diagram is shown in the following figure. S_AXI (slave) and M_AXI (master) AXI4 ports form an AXI Bridge that passes through authorized transactions and blocks unauthorized transactions. AXI Read and Write channels are completely independent of each other. If one channel is blocked for a violation, the other proceeds; if it does not trigger a violation.
The bridge relationship makes the XMPU_PL transparent to the system address mapping. Up-stream masters still map directly to down-stream slaves. Incoming transactions are subject to a two clock-cycle delay while the AXI-Monitor determines whether to allow or block. An example timing diagram is shown in the following figure.
Transactions between the upstream master and downstream slave are initiated by the master with the VALID signal. The XMPU_PL initially delays the transmission of the VALID signal to evaluate the transaction. If a transaction is not to be blocked (not poisoned) it proceeds without any additional or accumulative clock cycle latency. This results in all following transitions of signals are not delayed.
Each region in the XMPU_PL is independently activated and monitored. If a region is enabled and the requested transaction address is within its range, then the MasterID is compared to the enabled masters, and the AXI permissions are compared against the region’s configuration settings to determine if a violation has been triggered. If any region triggers a violation, then the transaction is blocked in accordance with the poisoning type configuration settings.
When a violation occurs, the status is communicated back to the Configuration Registers Module to capture the transaction’s target address and originating MasterID into the error status registers. If the violation corresponds to an enabled interrupt flag, then the ISR register is updated and the IRQ output is asserted.