XMPU_PL Configuration

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

Document ID
XAPP1353
Release Date
2022-05-04
Revision
v1.1 English

The XMPU_PL may be statically configured from the customization window in the IP Integrator. Refer to the Functional Description section for a detailed description of all the configuration registers. Alternatively, the XMPU_PL may be dynamically configured at run-time through the S_AXI_XMPU AXI4 slave port. While some of the run-time interface registers are read-only, their initialization values may be controlled through the static interface of the customization GUI.

S_AXI_XMPU has been implemented as an AXI4-Full I/F to ensure the Master ID of the originating AXI master is available within the transaction, via the AxUser bus. AxUser is collectively AWUSER and ARUSER for write and read transactions, respectively.

The Regions Max, S_AXI_ DATA_WIDTH, M_AXI_BASEADDR, and M_AXI_HIGHADDR values are VHDL parameters only and not available through the run-time interface.

Regions Max sets the number of AXI Monitors to be synthesized in the core. The SW cannot define more regions than this setting. The absolute maximum value is sixteen (16). Reducing this number decreases the utilized PL resources by ~130 LUTs per region. This parameter is exported to xparameters.h. Region configuration and Master IDs are explained in the following section.

S AXI DATA WIDTH sets the width of the AXI data bus to be protected. This must be selected by the user to match the upstream master. Available options are: 32, 64, 128-bit.

M AXI BASEADDR and M AXI HIGHADDR are not required to be set, and have no impact on the core’s functionality. Their presence is for the user’s convenience and they provide the address range mapped to M_AXI. These values are exported to the xparameters.h