Reference Design

Block-by-Block Configurable Fast Fourier Transform Implementation on AI Engine (XAPP1356)

Document ID
Release Date
1.0 English

Download the reference design files for this application note from the from the Xilinx® website.

Reference Design Matrix

The following checklist indicates the procedures used for the provided reference design. The reference design ZIP file contains a README that describes how to use the files.

Table 1. Reference Design Matrix
Parameter Description
Developer name Xilinx
Target devices Versal AI Core
Source code provided? Yes
Source code format (if provided) MATLAB script, AI Engine C code, and Makefile
Design uses code or IP from existing reference design, application note, 3rd party or Vivado software? AI Engine DSP Library (2020.2)
Functional simulation performed Yes
Timing simulation performed? No
Test bench provided for functional and timing simulation? No
Test bench format C Code
Simulator software and version AI Engine Simulator in Vitis™ unified software platform 2020.2
SPICE/IBIS simulations No
Implementation software tool(s) and version Vitis™ unified software platform 2020.2
Static timing analysis performed? No
Hardware Verification
Hardware verified? Yes
Platform used for verification VCK190