Block-by-Block Configurable Fast Fourier Transform Implementation on AI Engine (XAPP1356)

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The Fast Fourier Transform (FFT) is widely used in various signal processing algorithms which often require high throughput with configurable FFT sizes. This application note shows an efficient FFT implementation on the AI Engine arrays in Xilinx® Versal™ AI Core devices. The proposed architecture leverages the packet switching capability of the AI Engine array to distribute 4096 input samples to four AI Engines where 512- or 1024-point FFTs are performed, and then use another AI Engine to post-process the data for 2048- and 4096-point FFT according to a control word which specifies the FFT size and the FFT/IFFT mode on a block-by-block basis. Simulation results confirm that two FFT modules packed in a 5x2 AI Engine array achieve a 3.7 GSPS throughput, which is high enough to serve 24-32 antennas of 100 MHz bandwidth.

Download the reference design files for this application note from the from the Xilinx® website. For detailed information about the design files, see Reference Design.