Step 5: Floorplanning First Configuration

Isolation Design Flow + Dynamic Function eXchange Example Application Note (XAPP1361)

Document ID
XAPP1361
Release Date
2022-08-31
Revision
1.1 English

Open the synth dcp for floorplanning the first configuration (Config1). Ensure that the HD.ISOLATED is set to True for the following modules, static_iso_wrapper, rp1rm1/iso_2 and rp2rm1/iso_3.

  1. Assign package pins and I/O ports for the design. Run the following command from the Tcl console to assign package pins and I/O ports.
    source ./sources/pins.xdc
  2. Create Pblocks for Reconfigurable Partitions. Create a Pblock for rp1 and assign site ranges for the Pblock. Run the following command from the Tcl console to create a Pblock for the rp1.
    source ./sources/pb_rp_shift.xdc
  3. Similarly, create a Pblock for rp2 by running the following command from the Tcl console.
    source ./sources/pb_rp_count.xdc

    After running the floorplan, the device looks like Figure 1.

    Figure 1. Device View after the RP Floorplan
  4. Save the design. Run the DFX DRCs by opening Reports -> Report DRC…. Select DFX DRCs, and click OK to run the DRCs.
    Figure 2. DFX DRCs Selection Window

    After running the DFX DRCs, you can see there are no warnings or errors. There are two advisory messages. You can ignore those messages as they will resolve after creating the Pblock for the static region which is the static_iso_wrapper.

  5. Draw Pblocks for the Isolated Modules.
    1. Draw a Pblock for the static Isolated Module which is the static_iso_wrapper. Run the following command from the Tcl console.
      source ./sources/pb_iso_wrapper.xdc
    2. Draw a Pblock for the isolated module shift (iso_2) inside the Reconfigurable Partition rp1. Run the following command from the Tcl console:
      source ./sources/pb_shift_right.xdc
    3. Draw a Pblock for the Isolated Module count (iso_3) inside of the Reconfigurable Partitionrp2. Run the following command from the Tcl console:
      source ./sources/pb_count_up.xdc
    4. Save the constraints by saving the design.
      Note: Ignore the constraints order changed warning.
  6. Run VIV DRCs. These are IDF DRCs which are updated for the IDF+DFX flow. Under Report DRC, select IDF_VIV2-1, IDF_VIV2-2, IDF_VIV2-3 and IDF_VIV2-4 . Click OK to run the DRCs.
    Figure 3. IDF+DFX DRCs Selection Window
    Note: Do not select IDF_VIV2-5 and IDF_VIV2-6 as the design is not implemented yet. After the DRC run is completed you can see many IDF-4 violations, as shown in Figure 4.
    Figure 4. VIV Errors for PU Adjacency (IDF4_VIV2-4)
  7. Correct the floorplan violation.
    IDF highly recommends taking advantage of the highlighting features of the Vivado tools. The following Tcl script highlights all the Pblocks in the design:
    Set pblocks [get_pblocks *];set ci 1;foreach pblock $pblocks {highlight_objects -color_index [expr {1 + ($ci % 19)}] [get_pblocks $pblock]; incr ci}
    Shading the Pblocks tells the user what resources are included in it. Although, shading is visible when the Pblock is selected, highlighting it helps for better visibility. Additionally, it helps to differentiate between different Pblocks. In a highlighted Pblock, resources that have color are added to the Pblock, and the regions that are black are not included.

    Perform the following to correct the IDF violations.

    1. Click the first violation from the DRC report window. This selects the violating Programmable Units (PU) in the device view. Refer to Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335) for details on PU. You can select multiple violations to see the corresponding violating PUs.
      Figure 5. Violating PUs on Device View