The NIDRU described in this application note is optimized for the Versal device. This NIDRU operates on fractionally oversampled data and includes these features:
- Fully synchronous architecture based on DSP. It is based on a single clock tree even when multiple NIDRUs are instantiated and operating at different line rates.
- The input datapath width is programmable (DT_IN_WIDTH) and supports 4, 20, 32, 64, and 128 bits.
- The output datapath width is programmable (WDT_OUT) from 1 to 64 bits.
- The eye scan is fully DSP based. It is non-disruptive and does not use the eye scan logic that is built in the transceiver hardware.
- Rate, bandwidth, and jitter peaking are run-time programmable.
- Built in PPM meter, which measures run time difference between the incoming data rate and the local reference clock, with sub-PPM accuracy.
- Ability to synthesize the recovered clock on a separate transmitter (e.g., synchronization interfaces).
The application note is divided into the following sections:
- Use Model: general operating principles.
- Block Diagram and Pinout: attributes and ports of NIDRU are described.
- Configuration: a description of how to configure NIDRU ports and attributes.
- Simulating the NIDRU: a description of the NIDRU simulation test bench, with the settings of multiple line rates ready to be used.
- Versal ACAP Test Bench: a walk through of the NIDRU fully-featured demonstration on the VCK190 evaluation board, highlighting fractional operation, on-the-fly rate change and non-disruptive eye scan.