This section describes the operating principle of the NIDRU at a high level. The following figure illustrates the high-level application architecture for the NIDRU.
The fDIN data rate is the rate needed to receive and is generally lower than the rate the receiver can support normally. To receive data at a rate fDIN , the transceiver is set to operate at a rate fSAMPL , which is expected to be supported by the receiver and higher than fDIN .
The ratio fSAMPL /fDIN is defined as the oversampling rate (OR ) and it is recommended but not mandatory to keep it equal to at least 3 for reliable operation.
The transceiver is supposed to operate without tracking the data, a mode that is referred to as “Lock to Reference." In this mode, the transceiver operates as an A/D converter with a 1 bit resolution. For this reason, the NIDRU clock (fREFCLK ) is always locked to the PHY clock (fPHYCLK ) and is, consequently, part of the same clocking domain. As a result, a SelectIO can be used instead of a transceiver, as shown in the figure above.
EN_OUT is synchronized to the NIDRU clock. However, the rate at which EN_OUT is asserted by the NIDRU is locked to the remote clock domain (fDIN ).
The key feature of the NIDRU is that the ratio between the remote clock domain and the local clock domain (nominally, this ration is OR ) can be fractional, and the nominal ratio is specified using the port CENTER_F, as described later in this application note.
The most relevant consequence of this capability is that one single clock tree is needed, even if multiple NIDRUs are working at different line rates, provided all receivers are working at the same fSAMPL . See the following figure.