The QSPI controller is a hardened module inside the PMC, which is instantiated in the Vivado® Control, Interfaces, and Processing System (CIPS) IP. In the PMC functional block diagram, the QSPI controller is located at the PMC I/O peripherals, which includes the QSPI controller, OSPI controller, SD/EMMC controllers, I2C controller, and GPIO controller. The following figure shows that there is an NoC interconnect connected to the PMC through which the PL can access the QSPI controller.
Besides the Versal device internally accessing the QSPI controller path, on the other side, the host can access the Versal device NoC through the PCIe interface in the Versal device. Thus, the complete access path is as follows:
Host: PCIe RC > Versal device: PCIe EP (QDMA) > NoC > QSPI controller inside PMC > QSPI flash
The following figure shows the system architecture.
As shown in the figure, there are three types of datapath in the design:
- Blue Path: Host Access QSPI Controller
- This path is used to read and write QSPI controller registers. Thus, there
are two directions: one for write and another one for read.
Both Read Flash ID and Erase/Write Flash features are completed via this datapath. In a Read Flash ID, the host issues a series of QSPI controller register write and read operations until the QSPI Flash ID is obtained.
The Erase or Write QSPI Flash has a set of read and write operations. The main difference between Erase and Write operations is the content to write. Erase QSPI Flash writes zeroes to all QSPI flash, but the Write QSPI Flash operation writes specific content to the QSPI flash.
- Cyan Path: QSPI Controller DMA Read
- After the host issues a DMA read sequence to the QSPI controller via the blue path, the QSPI controller sends the data to the block RAM by the cyan path until the DMA data length reaches a defined size.
- Purple Path: Host Reads Back QSPI Flash Data in Block RAM
- All these three paths take in the Verify QSPI Flash operation. First, The QSPI command is sent through the blue path. Secondly, the QSPI controller uses DMA to send the data to block RAM via the cyan path. Finally, the host fetches the block RAM data through the purple data path, and then compares with the local memory data.
The reference design accompanying this application note includes a host software design and Versal ACAP hardware design (see Reference Design). The reference design is verified successfully in a X86 host and Xilinx VCK190 evaluation board environment. The Xilinx VCK190 evaluation board uses the Versal device XCVC1902.