Versal Device Hardware Design

Host Programming of QSPI Flash Host Programming of QSPI Flash (XAPP1372)

Document ID
XAPP1372
Release Date
2022-10-04
Revision
1.1 English

Block Design Introduction

It is assumed that customers use PCIe as a controller bus to connect the host (such as a x86 or Arm® processor) with the Versal device silicon. Normally, there are low bandwidth requirements, so GT Quad sharing with other protocols is realized, as an example.

In the block design (BD), PCIe Gen2 x1 and Aurora share the same GT Quad. PCIe integrated IP in the PL and QDMA AXI_bridge mode are used. In the following figure, AI Engine, DDR4, and Aurora are not involved in the host programming of QSPI flash.

Figure 1. Design Diagram

Four base address register (BAR) spaces are defined, as shown in the following figure. The first is BAR1, which is an AXI bridge master that connects to data storage spaces through the NOC (DDR4) and SmartConnect (block RAM). The second BAR is an AXI bridge master that accesses AI Engine space through the NoC. The third BAR is an AXI bridge master that connects to the QSPI controller through the NOC. The fourth BAR is an AXI4-Lite master space to access block RAM on the Versal device.

Figure 2. BAR Spaces

As the following address editor shows, BAR1 connects DDR, BAR2 connects AI Engine, and BAR3 connects PMC_SLAVES:

  • axi_noc_1/S09_AXI: BAR1 space: The reference design does not access this space.
  • ai_engine_0/S00_AXI: BAR2 space: The reference design does not access this space.
  • versal_cips_0/NOC_PMC_AXI_0/pspmc_0_psv_pmc_qspi_0: This is the QSPI controller space inside the PMC space.
  • versal_cips_0/NOC_PMC_AXI_0/pspmc_0_psv*: The reference design does not access these spaces.
Figure 3. Versal Device Address Editor

The following figure shows that BAR4 connects the block RAM controller. There is a space in the BAR4 that can be accessed by the host:

axi_bram_ctrl_0/S_AXI: This is the block RAM space that the host accesses through PCIe.

Figure 4. BAR4 Space

On the other hand, the block RAM controller connects with the dual-port block RAM to store QSPI flash data. The QSPI controller uses the DMA to transfer the data from QSPI flash to block RAM. There is another block RAM controller that connects the dual-port block RAM which reads out the QSPI flash data. There are two different addresses for the block RAM block. If the master is PCIe, the block RAM block’s address is 0xF000_0000. If the master is the QSPI controller in PMC, the address is 0x201_8000_0000. This is more than 32 bits of address space. Configuring this address to the QSPI controller register, DMA_Dst_Addr_L = 0x8000_0000 and DMA_Dst_Addr_H = 0x0000_0201.

Figure 5. BRAM Controller
Figure 6. Datapath inside PL Design

The host accesses the QSPI controller space by accessing BAR3. Data is transformed through the QDMA M_AXI_BRIDGE port, goes into the NoC slave port to the master port, and arrives at NOC_PMC_AXI_0.

The three colored datapaths are Versal device hardware datapaths in the entire system architecture. All the datapaths are identical in the whole design.

PCIe Debug Accessory

For easy debug of the PCIe link status, a PCIe specified debug hub and ILA are inserted in the BD.

Figure 7. PCIe Debug Hub and ILA
Figure 8. PCIe Debug Hub and ILA Path