Features

An arbitrary resampling filter is implemented on Xilinx AI Core devices with the following features:

• High performance with 16 taps and a 256x prestored filter coefficient look-up table
• Small footprint with three AI Engines packed in a 3x1 array supporting 250–350 MSPS input sample rates and a fixed output data rate at 500 MSPS synchronous to the output clock
• Sample-by-sample phase adjustment at a refined resolution of 1 ppb
• Deterministic output latency of 1 μs (exactly 500 clock cycles in the output clock domain)
• User-friendly FIFO-like input data and control interfaces
• Fully synchronous output interface with a solid-High valid signal and FIFO underflow flags
• Generic Makefile and Tcl scripts reusable by new designs with minor modification