Modern digital signal processing systems often support multiple communication protocols with various sample rates. However, in the analog front-end, most digital-to-analog (DAC) and analog-to-digital (ADC) converters only work at fixed sample rates. The following figure shows the block diagram of a typical software-defined radio system where a pair of arbitrary resampling filters (ARFs), one in the TX chain and the other in the RX, are employed to support various sample conversion ratios, which can be any real number within a certain range. The output sample rate of an ARF is refined to a small set of fixed data rates that can be efficiently handled by the digital up-conversion (DUC) and down-conversion (DDC) filters. Besides static sample rate conversion, ARFs are widely used for sampling clock error compensation without incurring a high phase noise.
The desirable features of the ARF come from its ability to handle dynamic timing offsets of output samples. In other words, the filter coefficients are computed in real-time for given timing offsets rather than in constants. This adds extra complexity to the ARF compared to normal filters. One strategy to lower the computational cost is to place ARFs as close to the baseband as possible, thus reducing the sample rate.
Several options for the ARF implementation in FPGAs have been discussed in Options for Arbitrary Resamplers in FPGA-Based Modulators [1]. Xilinx Versal AI Core devices offload the compute intensive part of the filter using AI Engine, while leaving the controller in the programmable logic (PL) for maximum flexibility (see Xilinx AI Engine and Their Applications (WP506)). The design of such a heterogeneous system is simplified by the Vitis software, which abstracts the design components as kernels interconnected by AXI buses. This application note provides an example of the design methodology described in Versal ACAP System and Solution Planning Methodology Guide (UG1504).