Multi-standard software defined radio systems employ arbitrary resampling filters to support a variety of sample rates. This application note shows the implementation of an arbitrary resampler on a Xilinx® Versal® AI Core device where the controller is in the programmable logic, and the heavy-lifting compute is mapped to the AI Engine. Integration and testing of such a heterogeneous system is simplified by the Xilinx Vitis™ software, which abstracts the processing units as kernels interconnected by AXI buses.
Download the reference design files for this application note from the Xilinx website. For detailed information about the design files, see Reference Design.