Power Domains

Simplified Power Sequencing (XAPP1375)
Document ID
XAPP1375
Release Date
2023-04-27
Revision
1.1 English

This section describes the basic functionality of the Versal device domains.

Platform Management Controller
The PMC is the first block to power on in the Versal device. This domain is responsible for booting and configuring the device and is similar to the power management unit (PMU) in previous AMD generations. This is the only domain of the Versal device that is required to be powered on at all times during operation. The PMC has multiple I/Os (banks 500, 501, and 503) that can be configured to signal to external sequencers or to the VRM enable pins directly to power on other domains or components in your system.
Low-power Domain
The LPD consists of a dual-core Arm® Cortex®-R5F real-time processor (RPU) for a multitude of functions. This block provides low power, low latency, and deterministic functions, and supports automotive safety integrity level (ASIL) and safety integrity level (SIL) functionality. It is common to have this domain powered up when the FPD, PL, and system domains are powered down for limited functionality and to maximize power savings. This domain also contains I/Os that can be programmed to enable regulators if I/Os in the PMC are not available.
Full-power Domain
The application processor (APU) in the FPD has a feature-rich dual-core Arm Cortex-A72 application processor. This domain is designed for complex algorithms, diverse decision trees, and has a broad set of libraries. It is common to have this domain powered up when the PL and system domains are powered down for limited functionality in addition to what can be achieved with the LPD processors.
Programmable Logic
The PL is the heart of Versal devices and contains the FPGA technology that can be precisely customized to a compute function and excels at latency critical real-time applications. It is common to power down the PL domain when not in use as it consumes a substantial amount of the device power even when idle due to the static power. This domain benefits the most from power management due to consuming most of the power in the Versal device.
System Domain
The system domain (SPD) powers the hardened memory controllers and network on chip (NoC), which is the high-speed integrated data path between the PL, PS, and other blocks within the Versal device. It must always be powered on when using the PL.