A modern power sequencing solution consists of multiple enable pins to signal a VRM to power up in the desired order at pre-defined time delays. The relative ramping of multiple power rails can impact the sequence seen at the target device.
A simultaneous ramp of two voltages at different target voltages can result in a sequence timing violation as seen at the target device. The time delay between the two simultaneous ramp rails can have a timing delta that falls outside the guidelines and results in an incorrect sequence. A ratiometric ramp is better suited to this kind of power up and should be considered when setting time delays and soft starts. The ramp up is timed to reach the target voltage at the same time as the power rail with the lower target voltage.
The AMD adaptive devices do not specify what time delta is acceptable for a ratiometric ramp of two rails sharing a power sequence slot. When two rails are assigned the same sequence slot, such as two different I/O supplies, the I/O supplies should reach their target voltages as close to the same time as can be achieved. However, if both rails reach the target voltage within the 0.2 ms to 40 ms timing slot and the next rail in the sequence (sequence slot 2) has not begun until all I/O supplies have reached their target voltage (sequence 1), the sequence is considered valid.
Sequential ramp voltages ramp up within sequence with a fixed delay between when the previous rail has reached its target voltage but might have differing slews. Voltage A in this scenario must wait until voltage B has reached at minimum 95% of target voltage before starting its own ramp.
AMD does not support any plateauing of voltage before it has reached its final value as this can lead to non-monotonic rises as shown in the following figure. A non-monotonic rise can produce unexpected results on the power rail and the rails might fail to reach the correct operating condition.
