Download the reference design files for this application note from the Xilinx website.
Reference Design Matrix
The following checklist indicates the procedures used for the provided reference design.
|Source code provided?
|Source code format (if provided)
|Design uses code or IP from existing reference design, application note, 3rd party or Vivado software? If yes, list.
|Partial reuse from PID Controller Design with Model Composer (XAPP1341)
|Functional simulation performed
|Timing simulation performed?
|Test bench provided for functional and timing simulation?
|Test bench format
|Simulator software and version
|2022.1 Xilinx Tools
|Synthesis software tools/versions used
|Implementation software tool(s) and version
|Static timing analysis performed?
|Platform used for verification
The reference design includes the following files:
- ClosedLoopPID_ACAP.slx: Single precision floating point PID controller using native VMC blocks, C++ based Math Sequencer, single channel AI Engine designs
- ClosedLoopPID_ACAP_rv2.slx: Single precision floating point PID controller example for both a single channel and a four channel AI Engine design
- ms.cpp, ms.h: PL-based Math Sequencer C++ source files
- PID.cc, PID_rv2.cc, PID.h: AI Engine C++ source files
- create_library.m: MATLAB file used to create the C++ simulatable Math Sequencer library block for use in a Simulink design