This application note is an extension to the PID Controller Design with Model Composer (XAPP1341), which targets the Versal® Adaptive Compute and Acceleration Platform (ACAP). With the introduction of the Versal AI Core series, Xilinx® customers have the option to perform native single precision floating-point (SPFP) operations in either the programmable logic (PL) or the AI Engines. This update demonstrates the Vitis™ Model Composer’s (VMC) flexibility to implement a floating point digital signal processing (DSP) algorithm targeting either a PL or an AI Engine implementation. A known golden reference Simulink® PID model demonstrates an independent method to validate and debug results for the two different PL implementations: VMC HLS blockset or C++ Based Math Sequencer and a single channel AI Engine implementation as shown in the following figure.
Figure 1. Multiple Approaches to Modeling an SPFP, Closed-Loop Control System