For device families prior to Versal® ACAPs, the JEDEC junction-to-board (θJB) and junction-to-case (θJC) resistance values are published in the appropriate packaging and pinouts user guide. They are generated by using the JEDEC specification boundary conditions, a small two signal, two power plane (2S2P) boards with mounted cold plates to represent close to infinite cooling. This can be useful at the very early stages of comparing packages within a product family or from multiple vendors, as it allows you to easily compare thermal parameters using common boundary conditions. However, it is not suggested to use these values for evaluating thermal performance in a given system due to the fact that the boundary conditions are very different from most realized environments. For a rough first pass evaluation of a device thermal performance in a given environment, it is suggested to obtain the modified θJC and θJB based on different h (W/m2 K) reflecting the system thermal design targets. This is documented in the appropriate thermal characterization document for your device/package, and can be obtained by request. This should give a more realistic high-level understanding of the amount of power dissipation that can be achieved with a given thermal solution or vice versa, the thermal solution that should be designed for a given power dissipation at a given ambient with minimal calculation. After this is understood and a more precise assessment is desired, it is suggested to use the Xilinx thermal models to get a more accurate view of the end thermal operation of the device/package.