As mentioned earlier, Xilinx recommends the use of an etching pattern on the contact surface of the heatsink, and it is even more important for bare die and lidless devices as a means to allow minimal BLT to the die. The thermal modeling of the etching is very difficult and can make meshing and computation time become excessive. For these reasons, when using etching, Xilinx recommends modeling a flat surface with very low BLT and/or slightly higher thermal conductivity than the TIM material provides by modeling it implicitly. For example, through experimental testing, it was determined for the Laird SP780 material, a modeled thickness of 70 um and conductivity of 20 W/mK would model the effectives of the etching. This is a simple way to understand the in-system benefits of the etching without the time and effort needed to properly model the etching.