Configuration

Non-Integer Data Recovery Unit (XAPP1362)

Document ID
XAPP1362
Release Date
2021-02-25
Revision
1.0 English

This section describes how to translate the incoming data rate and reference clock frequency into a valid NIDRU configuration.

The user configuration defines specifications for:

  • Incoming data rate with associated tolerance (f_DIN ± PPM)
  • Available reference clock frequency with associated tolerance (f_REFCLK ± PPM)

While f_DIN is given, f_REFCLK can be selected inside a valid range. The range upper limit comes from the necessity to close timing in the target device, and is thus device and speed grade dependent. The lower limit to f_REFCLK might be imposed by the PHY. For example, a SerDes typically specifies a minimum reference clock frequency. A SelectIO interface does not typically impose a lower limit to f_REFCLK . The maximum f_DIN is typically limited by the oversampling rate OR as defined in the following equation.

Recommended: Xilinx® recommends keeping OR ≥ 3 to have enough high frequency jitter tolerance.

CENTER_F, G1 and G2 should be set according to the following equations:

Using the equal value guarantees that the NIDRU operates in the lock-in region over the full PPM range of both the incoming data and the reference clock. Further reducing G_2 increases the NIDRU bandwidth. In general, increasing G_2 is not recommended, as the NIDRU would operate in pull-in region, where the automatic lock is not always guaranteed.

In general, G_(1_P) should be evaluated using the spreadsheet in the folder /excel_plots. The value should be increased up to when the ringing effect on the output phase becomes negligible. When G_1= G_2, setting G_(1_P)=16 always guarantees a negligible ringing effect. Consequently, G_(1_P)=16 is good for most of the cases.

The resulting transfer function can be obtained by using the excel file nidru_transfer_function_v_1_0.xls in the folder /excel_plots.

The usual three cases are considered as examples, yielding the following results:

  1. Fast Ethernet (fDIN =125 Mbit/s ± 100 PPM) with 125 MHz refclk (± 100 PPM):

    CENTER_F= b0000100000000000000000000000000000000

    G1 = G2 ≤ 11

  2. Fast Ethernet (fDIN =125 Mbit/s ± 100 PPM) with 155.52 MHz refclk (± 20 PPM):

    CENTER_F= b0000011001101110000101110010110101001

    G1 = G2 ≤ 11

  3. OC3 (fDIN =155.52 Mbit/s ± 20 PPM) with 125 MHz refclk (± 100 PPM):

    CENTER_F= b0000100111110100000010100010100001110

    G1 = G2 ≤ 11