The synthesis attributes for the DSP(s) in various modes are described in this section. The attributes call out pipeline registers in the control and datapaths. The value of the attribute sets the number of pipeline registers.
| Attribute Name | Settings (Default) | Description | ||
|---|---|---|---|---|
| DSP58 | DSPFP32 | DSPCPLX 1 | ||
| Register Control Attributes | ||||
| ACASCREG | 0, 1, 2 (1) 2 | Selects the number of A input registers on the A
cascade path, ACOUT. This attribute must be equal to or one less
than the AREG value: AREG = 0: ACASCREG must be 0 AREG = 1: ACASCREG must be 1 AREG = 2: ACASCREG can be 1 or 2 |
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| ADREG | 0, 1 (1) | N/A | 0, 1 (1) | Selects the number of AD pipeline registers. Because the common pre-adder output in CINT18 mode is registered in the AD registers of both DSPs, only a single ADREG attribute is used in CINT18. |
| ALUMODEREG | 0, 1 (1) | N/A | 0, 1 (1) | Selects the number of ALUMODE input registers. |
| AREG | 0, 1, 2 (1) | Selects the number of A input registers to the X multiplexer to the ALU or multiplier. For ALU, when 1 is selected, the A2 register is used. For multiplier, when 1 is selected and INMODE[0] = 1, A1 register is used. | ||
| BCASCREG | 0, 1, 2 (1) | N/A | 0, 1, 2 (1) | Selects the number of B input registers on the B
cascade path, BCOUT. This attribute must be equal to or one less
than the BREG value: BREG = 0: BCASCREG must be 0 BREG = 1: BCASCREG must be 1 BREG = 2: BCASCREG can be 1 or 2 (1 only in floating-point mode) |
| BREG | 0, 1, 2 (1) | N/A | 0, 1, 2 (1) | Selects the number of B input registers to the X multiplexer to the ALU or multiplier. For ALU, when 1 is selected, the B2 register is used. For multiplier, when 1 is selected and INMODE[4] = 1, B1 register is used. |
| CARRYINREG | 0, 1 (1) | N/A | 0, 1 (1) | Selects the number of programmable logic (PL) CARRYIN input registers. |
| CARRYINSELREG | 0, 1 (1) | N/A | 0, 1 (1) | Selects the number of CARRYINSEL input registers. |
| CREG | 0, 1 (1) | N/A | 0, 1 (1) | Selects the number of C input registers. |
| DREG | 0, 1 (1) | N/A | N/A | Selects the number of D input registers. |
|
DSP58/DSPFP32:INMODEREG DSPCPLX:CONJUGATEREG_A/ CONJUGATEREG_B |
0, 1 (1) | 0, 1 (1) | 0, 1 (1) | Selects the number of INMODE and NEGATE input registers. In DSPCPLX, the attribute is COJUGATEREG_A and CONJUGATEREG_B. |
| MREG | 0, 1 (1) | N/A | 0, 1 (1) | Selects the number of M pipeline registers. |
| OPMODEREG | 0, 1 (1) | N/A | 0, 1 (1) | Selects the number of OPMODE input registers. |
| RESET_MODE | SYNC, ASYNC (SYNC) | Selects if the enabled registers in the DSP are reset by their register specific synchronous resets or the common ASYNC_RST. | ||
|
DSP58, DSPCPLX: PREG DSPFP32: FPA_PREG, FPM_PREG |
0, 1 (1) | Selects the number of P output registers in non-floating-point mode (also used by CARRYOUT, PATTERNDETECT, PATTERNBDETECT, OVERFLOW, UNDERFLOW, XOROUT, CARRYCASCOUT, MULTSIGNOUT, and PCOUT). In DSPFP32, FPM_PREG and FPA_PREG select the identical number of registers for FPM and FPA respectively. | ||
| FPBREG | N/A | 0, 1 (1) | N/A | Selects number of B input registers in DSPFP32. |
| FPCREG | N/A | 0, 1, 2, 3 (3) | N/A | Selects number of C input registers in DSPFP32. |
| FPDREG | N/A | 0, 1 (1) | N/A | Selects number of D input registers in DSPFP32. |
| FPOPMREG | N/A | 0, 1, 2, 3 (3) | N/A | Select number of OPMODE input registers in DSPFP32. |
| FPMPIPEREG | N/A | 0, 1 (1) | N/A | Select number of M registers in DSPFP32 mode. |
| Feature Control Attributes | ||||
| DSP_MODE | INT24, INT8 (INT24) | (read only) | CINT18 | This attribute configures the DSP for a particular mode of operation. INT24 is for the 27 × 24 fixed-point ALU and also for the legacy mode. INT8 is for the three-element 9 × 8 vector dot-product mode. |
| A_INPUT | DIRECT, CASCADE (DIRECT) | Selects the A input between parallel input (DIRECT) or the cascaded input from the previous DSP (CASCADE). | ||
| B_INPUT | DIRECT, CASCADE (DIRECT) | Selects the B input between parallel input (DIRECT) or the cascaded input from the previous DSP (CASCADE). | ||
| BCASCSEL | N/A | B, D (B) | N/A | Selects cascade out data in DSPFP32 mode. |
| PCOUTSEL | N/A | FPM, FPA (FPA) | N/A | Select P cascade output data. |
| PREADDINSEL | A, B (A) | N/A | N/A | Selects the input to be added/subtracted with D in the pre-adder. |
| AMULTSEL | A, AD (A) | N/A | N/A | Selects the input to the 27-bit A input of the multiplier. |
| BMULTSEL | B, AD (B) | N/A | N/A | Selects the input to the 24-bit B input of the multiplier. |
| A_FPTYPE | N/A | B16, B32 (B32) | N/A | Selects floating-point data type for A. B16 is for binary16 (half-precision) and B32 is for binary32 (single-precision). |
| B_D_FPTYPE | N/A | B16, B32 (B32) | N/A | Selects floating-point data type for B and D for
multiplication. B16 is for binary16 (half-precision) and B32 is for
binary32 (single-precision). Note: When set to B16, D cannot be sent directly to
P1 for binary32 addition. It can be first multiplied by A = 1
and then sent to P0 as FPM for binary32 addition.
|
| USE_MULT | NONE, MULTIPLY (MULTIPLY) | NONE, MULTIPLY (MULTIPLY) | N/A | Selects usage of the multiplier. Set to NONE to save power when using only the Adder/Logic Unit in DSP58 or floating-point modes. |
| RND | 58-bit field (00...00) |
N/A | 58-bit field (00...00) |
This 58-bit value is used as the Rounding Constant into the WMUX. |
| USE_SIMD | ONE58, TWO24, FOUR12 (ONE58) | N/A | Selects the mode of operation for the adder/subtracter. The attribute setting can be one 58-bit adder mode (ONE58), two 24-bit adder mode (TWO24), or four 12-bit adder mode (FOUR12). Typical Multiply-Add operations are supported when the mode is set to ONE58. When either TWO24 or FOUR12 mode is selected, the multiplier must not be used, and USE_MULT must be set to NONE. | |
| USE_WIDEXOR | TRUE, FALSE (FALSE) | N/A | Determines whether the wide XOR is used or not used. | |
| XORSIMD | XOR12_22, XOR24_34_58_116 (XOR24_34_58_116) | N/A | Selects the mode of operation for the wide XOR. The attribute setting can be one 116-bit, two 58-bit, two 24-bit and two 34-bit XOR mode (XOR24_34_58_116), or six 12-bit and two 22-bit XOR mode (XOR12_22). | |
| Pattern Detector Attributes | ||||
| AUTORESET_PATDET | NO_RESET, RESET_MATCH, RESET_NOT_MATCH (NO_RESET) | N/A | NO_RESET, RESET_MATCH, RESET_NOT_MATCH (NO_RESET) | Automatically resets the P register (accumulated
value or counter value) on the next clock cycle, if a pattern detect
event has occurred on this clock cycle. The RESET_MATCH and
RESET_NOT_MATCH settings distinguish between whether the DSP58 must
cause an auto reset of the P register on the next cycle:
|
| AUTORESET_PRIORITY | RESET, CEP (RESET) | N/A | RESET, CEP (RESET) | When using the AUTORESET_PATDET feature, if the attribute is set to CEP, the P register only resets the pending value of the clock enable. Otherwise, the autoreset will have precedence. |
| MASK | 58‑bit field
(0011...11) |
N/A | 58‑bit field
(0011...11) |
This 58‑bit value is used to mask out certain bits during a pattern detection. When a MASK bit is set to 1, the corresponding pattern bit is ignored. When a MASK bit is set to 0, the pattern bit is compared. |
| PATTERN | 58‑bit field (00...00) |
N/A | 58‑bit field (00...00) |
This 58‑bit value is used in the pattern detector. |
| SEL_MASK | MASK, C, ROUNDING_MODE1, ROUNDING_MODE2 (MASK) | N/A | MASK, C, ROUNDING_MODE1, ROUNDING_MODE2 (MASK) | Selects the mask to be used for the pattern detector. The C and MASK settings are for standard uses of the pattern detector (counter, overflow detection, etc.). ROUNDING_MODE1 (C-bar left shifted by 1) and ROUNDING_MODE2 (C-bar left shifted by 2) select special masks based off of the optionally registered C input. These rounding modes can be used to implement convergent rounding in the DSP58 using the pattern detector. |
| SEL_PATTERN | PATTERN, C (PATTERN) | N/A | PATTERN, C (PATTERN) | Selects the input source for the pattern field. The input source can either be a 58-bit dynamic C input or a 58‑bit static attribute field. |
| USE_PATTERN_DETECT | NO_PATDET, PATDET (NO_PATDET) | N/A | NO_PATDET, PATDET (NO_PATDET) | Selects whether the pattern detector and related features, including overflow and underflow, are used (PATDET) or not used (NO_PATDET). This attribute is used for speed specification and Simulation Model purposes only. |
| Optional Inversion Attributes | ||||
| IS_ALUMODE_INVERTED | 4-bit binary (4’b0000) |
N/A | 4-bit binary (4’b0000) |
Indicates if the ALUMODE[3:0] is optionally
inverted within the DSP. The default 4’b0000 indicates that all bits of the ALUMODE bus are
not inverted. Each attribute bit controls its respective bit of the
ALUMODE bus. |
| IS_ASYNC_RST_INVERTED | 1-bit binary
(1’b0) |
Indicates if the ASYNC_RST is optionally
inverted within the DSP. The default 1’b0 indicates that the ASYNC_RST is not
inverted. |
||
| IS_CARRYIN_INVERTED | 1-bit binary (1’b0) |
N/A | 1-bit binary (1’b0) |
Indicates if the CARRYIN is optionally inverted
within the DSP. The default 1’b0
indicates that the CARRYIN is not inverted. |
| IS_CLK_INVERTED | 1-bit binary
(1’b0) |
Indicates if the CLK is optionally inverted
within the DSP. The default 1’b0
indicates that the CLK is not inverted. |
||
|
IS_INMODE_INVERTED IS_FPINMODE_INVERTED IS_CONJUGATE_INVERTED |
5-bit binary (5’b00000) |
1-bit binary (1’b0) |
1-bit binary (1’b0) |
Indicates if the INMODE[4:0] is optionally
inverted within the DSP. The default 5’b00000 indicates that all the bits of the INMODE bus
are not inverted. Each Attribute bit controls its respective bit of
the INMODE bus. In DSPFP32, the corresponding pin is FPINMODE. In
DSPCPLX, the corresponding pins are CONJUGATE_A and
CONJUGATE_B. |
| IS_NEGATE_INVERTED | 3-bit binary (1’b000) |
N/A | N/A | Indicates if all the bits of NEGATE are
optionally inverted within the DSP. The default 3’b000 indicates that the NEGATE[2:0]
is not inverted. |
|
IS_OPMODE_INVERTED IS_FPOPMODE_INVERTED |
9-bit binary
(9’b000000000) |
7-bit binary (7’b0000000) |
9-bit binary (9’b000000000) |
For DSP58 and DSPCPLX, indicates if the
OPMODE[8:0] is optionally inverted within the DSP. The default
9’b000000000 indicates that
all the bits of the OPMODE bus are not inverted. Each attribute bit
controls its respective bit of the OPMODE bus. In DSPFP32, the
corresponding pins are the FPOPMODE bus (7 bits). |
| IS_RSTA_INVERTED | 1-bit binary
(1’b0) |
Indicates if the RSTA is optionally inverted
within the DSP. The default 1’b0
indicates that the RSTA is not inverted. |
||
| IS_RSTALLCARRYIN_INVERTED | 1-bit binary (1’b0) |
N/A | 1-bit binary (1’b0) |
Indicates if the RSTALLCARRYIN is optionally
inverted within the DSP. The default 1’b0 indicates that the RSTALLCARRYIN is not
inverted. |
|
IS_RSTALUMODE_INVERTED IS_RSTFPA_INVERTED |
1-bit binary
(1’b0) |
Indicates if the RSTALUMODE is optionally
inverted within the DSP. The default 1’b0 indicates that the RSTALUMODE is not inverted. In
DSPFP32, the attribute IS_RSTFPA_INVERTED corresponds to the pin
RSTFPA. |
||
| IS_RSTB_INVERTED | 1-bit binary
(1’b0) |
Indicates if the RSTB is optionally inverted
within the DSP. The default 1’b0
indicates that the RSTB is not inverted. |
||
| IS_RSTC_INVERTED | 1-bit binary
(1’b0) |
Indicates if the RSTC is optionally inverted
within the DSP. The default 1’b0
indicates that the RSTC is not inverted. |
||
|
IS_RSTCTRL_INVERTED IS_RSTFPOPMODE_INVERTED |
1-bit binary
(1’b0) |
First attribute indicates if the RSTCTRL is
optionally inverted within the DSP. The default 1’b0 indicates that the RSTCTRL is not
inverted. Second attribute is for RSTFPOPMODE pin in
DSPFP32. |
||
|
IS_RSTD_INVERTED IS_RSTAD_INVERTED |
1-bit binary
(1’b0) |
IS_RSTD_INVERTED Indicates if the RSTD is
optionally inverted within the DSP. The default 1’b0 indicates that the RSTD is not
inverted. In DSPCPLX, the attribute IS_RSTAD_INVERTED corresponds to
the pin RSTAD. |
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|
IS_RSTINMODE_INVERTED IS_RSTFPINMODE_INVERTED IS_RSTCONJUGATE_INVERTED |
1-bit binary
(1’b0) |
The first attribute indicates if the RSTINMODE
is optionally inverted within the DSP. The default 1’b0 indicates that the RSTINMODE is
not inverted. IS_RSTFPINMODE_INVERTED attribute is for RSTFPINMODE
pin in DSPFP32. IS_RSTCONJUGATE_INVERTED is for RSTCONJUGATE pin in
DSPCPLX. |
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|
IS_RSTM_INVERTED IS_RSTFPMPIPE_INVERTED |
1-bit binary
(1’b0) |
Indicates if the RSTM is optionally inverted
within the DSP. The default 1’b0
indicates that the RSTM is not inverted. The attribute
IS_RSTFPMPIPE_INVERTED corresponds to RSTFPMPIPE pin in
DSP32. |
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|
IS_RSTP_INVERTED IS_RSTFPM_INVERTED |
1-bit binary
(1’b0) |
Indicates if the RSTP is optionally inverted
within the DSP. The default 1’b0
indicates that the RSTP is not inverted. The attribute
IS_RSTFPM_INVERTED corresponds to RSTFPM pin in DSPFP32. |
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