DSP Tile Pin | Direction | Bus Width (Default for DSP58) | DSP58 Unisim Pin | DSPCPLX Unisim Pin | DSPFP32 Unisim Pin | Description |
---|---|---|---|---|---|---|
A 1 | In | 34 | A[33:0] |
A_IM[17:0] 2 A_RE[17:0] |
A_SIGN A_EXP[7:0] A_MAN[22:0] |
A[26:0] is the A input of the multiplier or the A input of the pre-adder. A[33:0] are the most significant bits (MSBs) of the A:B concatenated input to the second-stage adder/subtracter or logic function. In INT8 mode (dot-product), port A holds three 9-bit two’s complement values or three unsigned 8-bit values by setting sign bits: A[26], A[17], and A[8] to 0. |
ACIN | In | 34 | ACIN[33:0] |
ACIN_IM[17:0] ACIN_RE[17:0] |
ACIN_SIGN ACIN_EXP[7:0] ACIN_MAN[22:0] |
Cascaded data input from ACOUT of previous DSP58 (multiplexed with A). |
ACOUT | Out | 34 | ACOUT[33:0] |
ACOUT_IM[17:0] ACOUT_RE[17:0] |
ACOUT_SIGN ACOUT_EXP[7:0] ACOUT_MAN[22:0] |
Cascaded data output to ACIN of the next DSP. |
ALUMODE | In | 4 | ALUMODE[3:0] |
ALUMODE_IM[3:0] ALUMODE_RE[3:0] |
N/A | Controls the selection of the logic and arithmetic function in the second stage add/sub/logic unit of the DSP. |
B | In | 24 | B[23:0] |
B_IM[17:0] B_RE[17:0] |
B_SIGN B_EXP[7:0] B_MAN[22:0] |
The B input of the multiplier or the B input of the preadder. B[23:0] are the least significant bits (LSBs) of the A:B concatenated input to the second-stage adder/subtracter or logic function. In INT8 mode (dot-product), port B holds three 8-bit two's complement values with sign bits B[23], B[15] and B[7]. |
BCIN | In | 24 | BCIN[23:0] |
BCIN_IM[17:0] BCIN_RE[17:0] |
BCIN_SIGN BCIN_EXP[7:0] BCIN_MAN[22:0] |
Cascaded data input from BCOUT of the previous DSP (multiplexed with B). |
BCOUT | Out | 24 | BCOUT[23:0] |
BCOUT_IM[17:0] BCOUT_RE[17:0] |
BCOUT_SIGN BCOUT_EXP[7:0] BCOUT_MAN[22:0] |
Cascaded data output to BCIN of the next DSP58. |
C | In | 58 | C[57:0] |
C_IM[57:0] C_RE[57:0] |
C[31:0] |
Data input to the second-stage adder/subtracter, pattern detector, or logic function. |
CARRYCASCIN | In | 1 | CARRYCASCIN |
CARRYCASCIN_IM CARRYCASCIN_RE |
N/A | Cascaded carry input from CARRYCASCOUT of the previous DSP58. |
CARRYCASCOUT | Out | 1 | CARRYCASCOUT |
CARRYCASCOUT_IM CARRYCASCOUT_RE |
N/A | Cascaded carry output to CARRYCASCIN of the next DSP. This signal is internally fed back into the CARRYINSEL multiplexer input of the same DSP. |
CARRYIN | In | 1 | CARRYIN |
CARRYIN_IM CARRYIN_RE |
N/A | Carry input from the logic. |
CARRYINSEL | In | 3 | CARRYINSEL[2:0] |
CARRYINSEL_IM[2:0] CARRYINSEL_RE[2:0] |
N/A | Selects the carry source. |
CARRYOUT | Out | 4 | CARRYOUT[3:0] |
CARRYOUT_IM CARRYOUT_RE |
FPA_INVALID, FPM_INVALID |
4‑bit carry output from each 12‑bit field of the accumulate/adder/logic unit. Normal 58-bit operation uses only CARRYOUT[3]. Only the SIMD mode FOUR12 can use all the four CARRYOUT bits (CARRYOUT[3:0]). In DSPFP32 mode: FPA_INVALID is mapped to CARRYOUT[1] FPM_INVALID is mapped to CARRYOUT[0] In DSPCPLX mode CARRYOUT[3] is used as CARRYOUT_RE and CARRYOUT_IM |
CEA1 | In | 1 | CEA1 |
CEA1_IM CEA1_RE |
CEA1 | Clock enable for the first A (input) register. A1 is only used if AREG = 2 or INMODE[0] = 1. INMODE control is for multiplier only. |
CEA2 | In | 1 | CEA2 |
CEA2_IM CEA2_RE |
CEA2 | Clock enable for the second A (input) register. A2 is only used if AREG = 1 or 2 and INMODE[0] = 0. INMODE control is for multiplier only. |
CEAD | In | 1 | CEAD | CEAD | N/A | Clock enable for the pre-adder output AD pipeline register. |
CEALUMODE | In | 1 | CEALUMODE |
CEALUMODE_IM CEALUMODE_RE |
CEFPA | Clock enable for ALUMODE (control inputs) registers. In DSPFP32 this is the clock enable for the FPA output registers. |
CEB1 | In | 1 | CEB1 |
CEB1_IM CEB1_RE |
CEB | Clock enable for the first B (input) register. B1 is only used if BREG = 2 or INMODE[4] = 1. In DSPFP32 there is only one B input so CEB1 is renamed CEB. INMODE control is for multiplier only. |
CEB2 | In | 1 | CEB2 |
CEB2_IM CEB2_RE |
N/A | Clock enable for the second B (input) register. B2 is only used if BREG = 1 or 2 and INMODE[4] = 0. In DSPFP32 there is only one B input so no CEB2 pin is available. INMODE control is for multiplier only. |
CEC | In | 1 | CEC |
CEC_IM CEC_RE |
CEC | Clock enable for the C (input) register. In DSPFP32, CEC enables all C register stages configured by the FPCREG attribute. |
CECARRYIN | In | 1 | CECARRYIN |
CECARRYIN_IM CECARRYIN_RE |
N/A | Clock enable for the CARRYIN (input from the logic) register. |
CECTRL | In | 1 | CECTRL |
CECTRL_IM CECTRL_RE |
CEFPOPMODE | Clock enable for the OPMODE and CARRYINSEL (control inputs) registers. |
CED | In | 1 | CED | N/A | CED | Clock enable for the D (input) register. |
CEINMODE | In | 1 | CEINMODE |
CECONJUGATE_A CECONJUGATE_B |
CEFPINMODE | Clock enable for the INMODE control input registers. Also the clock enable for NEGATE control input registers in DSP58 mode and for CONJUGATE_A/B input registers in DSPCPLX mode. |
CEM | In | 1 | CEM |
CEM_IM CEM_RE |
CEFPMPIPE | Clock enable for the post-multiply M (pipeline) register and the internal multiply CARRYIN register (DSP58, DSPCPLX only). |
CEP | In | 1 | CEP |
CEP_IM CEP_RE |
CEFPM | Clock enable for the P output register in DSP58/DSPCPLX and FPM output register in DSPFP32. |
CLK | In | 1 | CLK | CLK | CLK | The DSP58 input clock, common to all internal registers and flip-flops. |
D | In | 27 | D[26:0] | N/A |
D_SIGN D_EXP[7:0] D_MAN[22:0] |
27-bit input to the pre-adder. The pre-adder implements D ± A or D ± B as determined by the attribute PREADDINSEL. The INMODE[3] signal determines whether the pre-adder is performing an addition or subtraction. In DSPFP32, this port is an alternative input to the floating-point multiplier (binary16 or binary32), or binary32 input to the standalone binary 32 adder. |
INMODE | In | 5 | INMODE[4:0] |
CONJUGATE_A CONJUGATE_B |
FPINMODE | These five control bits select the functionality of the pre-adder, the A, B, and D inputs, and the input registers. These bits should be tied to GND if unused. In DSPCPLX INMODE[3] only is used and mapped to CONJUGATE. In DSPFP32 INMODE[4] is mapped to FPINMODE and controls input MUX selection between B and D input ports to FP Multiplier. |
MULTSIGNIN | In | 1 | MULTISIGNIN |
MULTISIGNIN_IM MULTISIGNIN_RE |
N/A | Signal from the previous DSP for MACC extension. |
MULTSIGNOUT | Out | 1 | MULTISIGNOUT |
MULTISIGNOUT_IM MULTISIGNOUT_RE |
N/A | Signal cascaded to the next DSP for MACC extension. |
NEGATE | In | 3 | NEGATE[2:0] | N/A | N/A | Select if the multiplier input needs to be negated. In DSPCPLX, the CONJUGATE inputs connected to INMODE[3] is used. For DSP58, in INT24 mode, only NEGATE[0] is used. In INT8 mode, all NEGATE bits are used. |
OPMODE | In | 9 | OPMODE[8:0] |
OPMODE_IM[8:0] OPMODE_RE[8:0] |
FPOPMODE[6:0] | Controls the input to the W, X, Y, and Z multiplexers in DSP58 and DSPCPLX Unisims only. In DSPFP32 the lower 7 bits control the P0 and P1 inputs to the floating point adder. |
OVERFLOW | Out | 1 | OVERFLOW |
OVERFLOW_IM OVERFLOW_RE |
FPA_OVERFLOW | Overflow indicator when used with the appropriate setting of the pattern detector. In DSPFP32, this flag indicates overflow of the floating-point adder. |
P | Out | 58 | P[57:0] |
P_IM[57:0] P_RE[57:0] |
{FPM_OUT [25:0] FPA_OUT[31:0]} | Data output from second stage adder/subtracter or logic. In DSPFP32, bits [57:32] are mapped to floating point multiplier (FPM), and bits [31:0] are mapped to the output of the floating point adder (FPA). |
PATTERNBDETECT | Out | 1 | PATTERNBDETECT |
PATTERNBDETECT_IM PATTERNBDETECT_RE |
N/A | Match indicator between P[57:0] and the complement of the pattern. |
PATTERNDETECT | Out | 1 | PATTERNDETECT |
PATTERNDETECT_IM PATTERNDETECT_RE |
N/A | Match indicator between P[57:0] and the pattern. |
PCIN | In | 58 | PCIN[57:0] |
PCIN_IM[57:0] PCIN_RE[57:0] |
PCIN[31:0] | Cascaded data input from PCOUT of the previous DSP58 to ALU. In floating-point mode, only the lower 32 bits are used and the upper 26 bits are set to zero. |
PCOUT | Out | 58 | PCOUT[57:0] |
PCOUT_IM[57:0] PCOUT_RE[57:0] |
PCOUT[31:0] | Cascaded data output to PCIN of the next DSP58. In DSPFP32, only the lower 32 bits are used. |
RSTA | In | 1 | RSTA |
RSTA_IM RSTA_RE |
RSTA | Reset for both A (input) registers. |
RSTALLCARRYIN | In | 1 | RSTALLCARRYIN |
RSTALLCARRYIN_IM RSTALLCARRYIN_RE |
N/A | Reset for the Carry (internal multiply round) and the CARRYIN register in all fixed-point modes. |
RSTALUMODE | In | 1 | RSTALUMODE |
RSTALUMODE_IM RSTALUMODE_RE |
RSTFPA | Reset for ALUMODE (control inputs) registers. In DSPFP32 acts as reset for FPA output registers |
RSTB | In | 1 | RSTB |
RSTB_IM RSTB_RE |
RSTB | Reset for both B (input) registers. |
RSTC | In | 1 | RSTC |
RSTC_IM RSTC_RE |
RSTC | Reset for the C (input) register. |
RSTCTRL | In | 1 | RSTCTRL |
RSTCTRL_IM RSTCTRL_RE |
RSTFPOPMODE | Reset for OPMODE and CARRYINSEL (control inputs) registers. |
RSTD | In | 1 | RSTD | N/A | RSTD | Reset for the D (input) register. |
RSTAD | In | 1 | N/A | RSTAD | N/A | Reset for the pre-adder (output) AD pipeline register. |
RSTINMODE | In | 1 | RSTINMODE |
RSTINMODE_IM RSTINMODE_RE |
RSTFPINMODE | Reset for the INMODE (control input) registers. |
RSTM | In | 1 | RSTM |
RSTM_IM RSTM_RE |
RSTFPMPIPE | Reset for the M (pipeline) register. |
RSTP | In | 1 | RSTP |
RSTP_IM RSTP_RE |
RSTFPM | Reset for P output registers in DSP58 and DSPCPLX, and reset for FPM output registers in DSPFP32. |
ASYNC_RST | In | 1 | ASYNC_RST | ASYNC_RST | ASYNC_RST | Asynchronous reset for all registers. Input only valid when attribute RESET_MODE = ASYNC. |
UNDERFLOW | Out | 1 | UNDERFLOW |
UNDERFLOW_IM UNDERFLOW_RE |
FPA_UNDERFLOW | Underflow indicator when used with the appropriate setting of the pattern detector. In DSPFP32, this flag indicates underflow of the floating-point adder. |
XOROUT | Out | 8 | XOROUT[7:0] |
XOROUT_IM[7:0] XOROUT_RE[7:0] |
{FPM_UNDERFLOW FPM_OVERFLOW, FPM_OUT [31:26]} | Data output from wide XOR function. In DSPFP32: XOROUT[5:0] are mapped to FPMOUT[31:26], XOROUT[6] is mapped to overflow status port for FP multiplier and XOROUT[7] is mapped to the underflow status port of the FP multiplier. |
|