DSPCPLX Pipeline Configuration

In the CINT18 mode, the complete implementation of the complex multiplication algorithm requires the preadders and multipliers in both the DSP58s to work together thereby allowing only specific pipeline configurations to be valid. Programming for each pipeline stage visible to the user in the DSPCPLX Unisim is allowed. However, invalid attribute values generate a software DRC that instructs the user to change their attribute settings. The following two tables specify the valid attribute values for the complex mode for the case with balanced inputs and the case where the inputs are required to be balanced in the programmable logic. Note that any input pipeline combination other than those specified in these tables are invalid and the operands will not line up properly with invalid results. The figure that follows illustrates a simplified block diagram of the complex multiply accumulator.

Note: The conjugate inputs labeled as *_A and *_B are intended to demonstrate that these are relative to the two complex inputs rather than the real and imaginary parts. Also, the labels A_RE, B_RE, A_IM, and B_IM show the side the signals come in physically. Internally the signals go to both DSP58s.

Table 1. CINT18 Mode Programmable Register Attributes (valid use cases with balanced inputs)
AREG_RE	BREG_RE	ADREG	AREG_IM	BREG_IM	Notes	Register Delay Required on CONJUGATE Inputs (RE and IM)²	Latency (from Input pin to MREG input)
0	0	0	0	0	Valid Case, All REG bypassed	0	0
1	1	0	1	1	Valid Case balanced pipeline¹	1	1
2	2	1	2	2	Valid Case, fully pipelined mode	1	2
When ADREG is set to 0, DSP internally selects the output of the first register of the two-stage input pipeline of AREG and BREG registers. The value of the register delay required on the CONJUGATE inputs (both RE and IM) can be achieved by either setting CONJUGATEREG = 1 or balancing the inmode input in the programmable logic (PL) by one clock cycle (adding latency in the PL and setting CONJUGATEREG = 0).

Table 2. CINT18 Mode Programmable Register Attributes (valid use cases that require inputs to be balanced in PL)
AREG_RE	BREG_RE	ADREG	AREG_IM	BREG_IM	Notes¹	Register Delay Required on CONJUGATE Inputs (RE and IM)²	Latency (from Input pin to MREG input)
0	0	0	0	1	A_RE,B_RE,A_IM inputs need to be balanced in the logic by 1 clk cycle.	0	1 (from B_IM pin)
0	1	0	0	0	A_RE,B_IM,A_IM inputs need to be balanced in the logic by 1 clk cycle.	0	1 (from B_RE pin)
0	1	0	0	1	A_RE, A_IM inputs need to be balanced in the logic by 1 clk cycle.	0	1 (from B_RE and B_IM pins)
1	0	0	1	0	B_RE, B_IM inputs need to be balanced in the logic by 1 clk cycle	1	1 (From A_RE and A_IM pins)
1	0	0	1	1	B_RE input needs to be balanced in the logic by 1 clk cycle	1	1 (From A_RE, A_IM and B_IM pins)
1	1	0	1	0	B_IM input needs to be balanced in the logic by 1 clk cycle	1	1 (From A_RE, B_RE, A_IM pins)
1	2	0	1	0	BREG_IM input needs to be balanced in the logic by 1 clk cycle	1	1 (From A_RE, B_RE, A_IM pins)
1	0	0	1	2	BREG_RE input needs to be balanced in the logic by 1 clk cycle	1	1 (From A_RE, A_IM, B_RE Pins)
Condition where balance of inputs is needed ADREG == 0 && { [(AREG_RE==0 && AREG_IM==0) && (BREG_RE==1 \|\| BREG_IM==1)] \|\| [(AREG_RE==1 && AREG_IM==1) && (BREG_RE==0 \|\| BREG_IM==0)] } The value of the register delay required on the CONJUGATE inputs (both RE and IM) can be achieved by either setting CONJUGATEREG = 1 or balancing the inmode input in the programmable logic (PL) by one clock cycle (adding latency in the PL and setting CONJUGATEREG = 0).

Figure 1. CINT18 Mode 18 × 18 Complex Multiplier and 58 + 58 Complex Accumulator Simplified Block Diagram

CE Usage in DSPCPLX Configuration

CE usage in DSPCPLX configuration is described as follows:

Balanced Pipeline (case 2): Only CEA1 and CEB1 (_RE/_IM) are needed to ensure functionality.

Fully Pipeline (case 3): CEA1, CEA2, CEB1 and CEB2 are required to ensure functionality.

Cascade path where ACOUT/BCOUT goes externally to the next DSPCPLX in the cascade: ACASCREG and BCASCREG are set accordingly to the Attribute Setting Description table in Attributes.

ACASCREG = 1: CEA1 is required to ensure functionality.

ACASCREG = 2: CEA2 is required to ensure functionality.

BCASCREG: CEB2 is required to ensure functionality, except when BCASCREG=1 and BREG=2 where CEB1 is required.