System Design Types - 2021.2 English

Versal® ACAP is a heterogeneous compute platform with multiple compute engines. A wide range of applications can be mapped on Versal ACAP, including signal processing for wireless systems, machine learning inference, and video processing algorithms. In addition to multiple compute engines, Versal ACAP offers very high system bandwidth using high-speed serial I/Os, network on chip (NoC), DDR4/LPDDR4 memory controllers, and multi-rate Ethernet Media Access Controllers (MRMACs). Versal devices are categorized into the Versal Prime, Premium, and AI Core series. The following figure shows the different system design types and design flows supported for each Versal device series.

Figure 1. System Design Types

The following table shows the system design types and design flows supported for each Versal device series. As shown in the table, a majority of the design flows are based on building a platform.

Following is a summary of each system design type:

Hardware-only system

Programmable logic designs. Create this system using the traditional design flow.

Embedded system

Embedded processing system with software running on the Arm® Cortex®-A72 and Cortex-R5F processors and hardware content in the PL. Create this system using either the traditional or platform-based design flow.

Embedded AI Engine system

Embedded processing system with software running on the Arm Cortex-A72 and Cortex-R5F processors, hardware content in the PL, and algorithmic content in the AI Engine. Create this system using the platform-based design flow.

Following are the design flows for Versal ACAP:

Traditional design flow (no platform)

In the traditional design flow, the entire PL portion of the system is defined in a single Vivado® project. This project must include the foundational Versal hardware IP blocks (e.g., Control, Interface, and Processing System (CIPS), NoC, I/O controllers) and any other custom RTL and IP blocks needed for the project. Design sources are added to the Vivado tools and compiled through the Vivado implementation flow. If the system consists of PL components only, the Vivado tools are used to generate a programmable device image (PDI) to program the Versal device. If the system also includes embedded software content, the software application is developed in the Vitis™ environment on top of the fixed hardware design exported from the Vivado tools. This flow is similar to the one traditionally used for Zynq® UltraScale+™ MPSoCs.

Platform-based design flow (custom platform)

In the platform-based design flow, the system is divided in two distinct elements: the platform and the processing system. The platform is a well-formalized design resource that contains the foundational Versal hardware IP blocks (e.g., CIPS, NoC, I/O controllers) and software features (e.g., domains, device tree, OS) upon which a complete working system can be built and integrated. The hardware part of the platform is a dedicated Vivado project containing the minimum necessary hardware IP blocks. The software components are packaged with the hardware to create a custom platform. The processing system consists of PS, PL, and optional AI Engine features that implement the main functionality of the system. These different elements can be created with the Vivado tools or the Vitis environment. These elements are then integrated to the platform using the Vitis environment. This flow promotes concurrent development of the different elements of the system and facilitates the integration process of heterogeneous systems.