ユーザー パラメーター - 1.0 日本語

Clocking Wizard v1.0 for Versal ACAP LogiCORE IP 製品ガイド (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 日本語

次の表に、 Vivado® IDE のフィールドとユーザー パラメーターの対応関係を示します。ユーザー パラメーターは Tcl (Tool Command Language) コンソールで表示できます。

表 1. ユーザー パラメーターの説明
Vivado IDE のパラメーター/値 ユーザー パラメーター/値 デフォルト値
[Component Name] COMPONENT_NAME Clk_wizard_0
[Primitive]

値: MMCM、PLL、DPLL、Auto、None

PRIMITIVE_TYPE MMCM
[Phase Alignment]

値: TRUE、FALSE

USE_PHASE_ALIGNMENT FALSE
[Minimize Power]

値: TRUE、FALSE

USE_MIN_POWER FALSE
[Jitter Optimization]

値:

JITTER_SEL Balanced
表示名 実際の値
Balanced No_Jitter
Minimize Output Jitter Min_O_Jitter
Maximize Input Jitter filtering Max_I_Jitter
[Secondary]

値: TRUE、FALSE

USE_INCLK_SWITCHOVER FALSE
[Port Name]

PRIMARY_PORT、

SECONDARY_PORT

PRIMARY_PORT Clk_in1

SECONDARY_PORT Clk_in2

[Primary]: [Input Frequency (MHz)]

値 (デフォルト): 10 ~ 1230 (値の範囲は、選択したデバイス/ボードのタイプにより異なります)

PRIM_IN_FREQ 100.000
[Secondary]: [Input Frequency (MHz)]

値 (デフォルト): 72 ~ 144

SECONDARY_IN_FREQ 100.000
[Jitter Options]

値: UI、PS

JITTER_OPTIONS UI
[Primary]: [Input Jitter]

値:

PS: [10 ~ 999] UI: [0.001 ~ 0.10]

CLKIN1_JITTER 0.010
[Secondary]: [Input Jitter]

値:

UI: [0.001 ~ 0.10]

PS: [10 ~ 999]

CLKIN2_JITTER 0.010
[Source]

値:

  • 1-Single ended Clock Capable pin
  • 2-Differential ended Clock capable pin
  • 3-Global Buffer
  • 4-No Buffer
PRIM_SOURCE Single ended clock capable pin
[Source]

値:

  • 1-Single ended Clock Capable pin
  • 2-Differential ended Clock capable pin
  • 3-Global Buffer
  • 4-No Buffer
SECONDARY_SOURCE Single ended clock capable pin
[Clk_out<1-7>]

値: TRUE、FALSE

CLKOUT_USED TRUE、FALSE、FALSE、FALSE、FALSE、FALSE、FALSE
[Port Name]

値: TRUE、FALSE

CLKOUT_PORT clk_out1clkout2clk_out3clk_out4clk_out5clk_out6clk_out7
[Requested Output clock frequency] CLKOUT_REQUESTED_OUT_FREQ 100.000、100.000、100.000、100.000、100.000、100.000、100.000
[Requested Phase]

値: -360 ~ 360

CLKOUT_REQUESTED_PHASE 0.000、0.000、0.000、0.000、0.000、0.000、0.000
[Requested Duty Cycle]

値: 0.001 ~ 99.99

CLKOUT_REQUESTED_DUTY_CYCLE デフォルト値: 50.0、50.0、50.0、50.0、50.0、50.0、50.0
[Drives]

値: BUFG、BUFGCE、BUFGCE_DIV、MBUFGCE、Buffer、Buffer with CE、No_buffer

CLKOUT_DRIVES BUFG、BUFG、BUFG、BUFG、BUFG、BUFG
[PI Control]

値: DESKEW_PD1、DESKEW_PD2、Fine_PS、None

CLKOUT_DYN_PS None、None、None、None、None、None、None
[Clock Grouping]

値: Auto、CLOCK_A、CLOCK_B、CLOCK_C、None

CLKOUT_GROUPING Auto、Auto、Auto、Auto、Auto、Auto、Auto
[Source]

値:

FEEDBACK_SOURCE Automatic Control On-Chip
表示名 実際のパラメーター
Automatic Control On-Chip FDBK_AUTO
Automatic Control Off-Chip FDBK_AUTO_OFFCHIP
User-Controlled On-Chip FDBK_ONCHIP
User-Controlled Off-Chip FDBK_OFFCHIP
[Signaling]

値:

- Single-ended: SINGLE

- Differential: DIFF

CLKFB_IN_SIGNALING Single-ended
[Reset]

値: TRUE、FALSE

USE_RESET False
[Powerdown]

値: TRUE、FALSE

USE_POWER_DOWN False
[Input clk stopped]

値: TRUE、FALSE

USE_INCLK_STOPPED False
[Locked]

値: TRUE、FALSE

USE_LOCKED False
[Locked_FB]

値: TRUE、FALSE

USE_LOCKED_FB False
[Locked_DESKEW1]

値: TRUE、FALSE

USE_LOCKED_DESKEW1 False
[Locked_DESKEW2]

値: TRUE、FALSE

USE_LOCKED_DESKEW2 False
[deskew1_delay_en]

値: TRUE、FALSE

DESKEW1_DELAY_EN False
[deskew2_delay_en]

値: TRUE、FALSE

DESKEW2_DELAY_EN False
[deskew1_delay_path]

値: ClkIn Path、ClkFb Path

DESKEW1_DELAY_PATH ClkFb Path
[deskew1_delay]

値: 0 ~ 63

DESKEW1_DELAY 0
[deskew2_delay_path]

値: ClkIn Path、ClkFb Path

DESKEW2_DELAY_PATH ClkFb Path
[deskew2_delay]

値: 0 ~ 63

DESKEW2_DELAY 0
[Clkfbstopped]

値: TRUE、FALSE

USE_CLKFB_STOPPED False
[Reset Type]

値: active-High、active-Low

RESET_TYPE active-High
[Phase shift Mode]

値: WAVEFORM、LATENCY

PHASESHIFT_MODE LATENCY
[Allow Override Mode]

値: TRUE、FALSE

OVERRIDE_PRIMITIVE False
[BANDWIDTH]

値:

MMCM: LOW、HIGH、OPTIMIZED

PLL: LOW、HIGH、OPTIMIZED

DPLL: OPTIMIZED

BANDWIDTH OPTIMIZED
[CLKFBOUT_MULT]

値: 選択したプリミティブにより異なります

CLKFBOUT_MULT 30
[CLKFBOUT_PHASE]

値: (-360.000:360.00)

CLKFBOUT_PHASE 0.000
[COMPENSATION]

値:

DPLL: INTERNAL AUTO、BUF_IN、EXTERNAL

PLL: INTERNAL

MMCM: AUTO、INTERNAL、BUF_IN、EXTERNAL

COMPENSATION AUTO
[DIVCLK_DIVIDE]

値: 選択したプリミティブにより異なります

DIVCLK_DIVIDE 1
[CLKFBOUT_PHASE_CTRL]

値: None、Fine_PS、DESKEW_PD1、DESKEW_PD2

CLKOUTFB_PHASE_CTRL None
[Divide] CLKOUT<1-7>_DIVIDE 30
[Duty Cycle]

値: 0 ~ 100

CLKOUT<1-7>_DUTY_CYCLE 0.500
[Phase]

値: -360 ~ 360

CLKOUT<1-7>_PHASE 0.000
[Locked] LOCKED_PORT Locked
[Clk_in_sel] CLK_IN_SEL_PORT Clk_in_sel
[Reset] RESET_PORT reset
[Input_clk_stopped] INPUT_CLK_STOPPED_PORT Input_clk_stopped
[Clkfb_stopped] CLKFB_STOPPED_PORT Clkfb_stopped
[Locked_FB] LOCKED_FB_PORT locked_fb
[Locked_DESKEW1] LOCKED_DESKEW1_PORT locked_deskew1
[Locked_DESKEW2] LOCKED_DESKEW2_PORT locked_deskew2
[Power_Down] POWER_DOWN_PORT power_down
[Dynamic Reconfig]

値: TRUE、FALSE

USE_DYN_RECONFIG FALSE
[Spread Spectrum]

値: TRUE、FALSE

USE_SPREAD_SPECTRUM FALSE
[Enable Clock Monitoring]

値: TRUE、FALSE

ENABLE_CLOCK_MONITOR FALSE
[ZHOLD]

値: TRUE、FALSE

ZHOLD FALSE
[Ss Mode]

値:

  • CENTER HIGH
  • CENTER LOW
  • DOWN HIGH
  • DOWN LOW
SS_MODE CENTER HIGH
[Modulation Freq]

値: 25 ~ 250

SS_MOD_FREQ 250
[Dynamic Reconfig Interface Options]

値: Enable_AXI、Enable_APB3

INTERFACE_SELECTION Enable_AXI
[Enable User Clock0]

値: TRUE、FALSE

ENABLE_SUER_CLOCK0 FALSE
[Enable User Clock1]

値: TRUE、FALSE

ENABLE_SUER_CLOCK1 FALSE
[Enable User Clock2]

値: TRUE、FALSE

ENABLE_SUER_CLOCK2 FALSE
[Enable User Clock3]

値: TRUE、FALSE

ENABLE_SUER_CLOCK3 FALSE
[User clk0 Freq]

値: 1 ~ 300

USER_CLK_FREQ0 100
[User clk1 Freq]

値: 1 ~ 300

USER_CLK_FREQ1 100
[User clk2 Freq]

値: 1 ~ 300

USER_CLK_FREQ2 100
[User clk3 Freq]

値: 1 ~ 300

USER_CLK_FREQ3 100
[Enable PLL0]

値: TRUE、FALSE

Enable_PLL0 FALSE
[Enable PLL1]

値: TRUE、FALSE

Enable_PLL1 FALSE
[Ref clk Freq]

値: 1 ~ 300

REF_CLK_FREQ 100
[Precision]

値: 1 ~ 100

PRECISION 1
[Relative Inclk]

値: REL_PRIMARY、REL_SECONDARY

RELATIVE_INCLK REL_PRIMARY
[Deskew1 IN]

値: 0 ~ 9

DESKEW1_IN 0
[Deskew1 FB]

値: 1 ~ 7

DESKEW1_FB 1
[Deskew2 IN]

値: 0 ~ 9

DESKEW2_IN 0
[Deskew2 FB]

値: 1 ~ 7

DESKEW2_FB 1
[Safe Clock Startup]

値: TRUE、FALSE

USE_SAFE_CLOCK_STARTUP FALSE
[Safe Clock Startup Mode]

値: DESKEW_MODE、BUFGCE_MODE

SAFECLOCK_STARTUP_MODE DESKEW_MODE
[CE TYPE]

値: SYNC、ASYNC、HARDSYNC

CE_TYPE SYNC
[BUFGCE DIV CE TYPE]

値: SYNC、HARDSYNC

BUFGCE_DIV_CE_TYPE SYNC
[CE and CLR SYNC Circuit External to Core]

値: FALSE、TRUE

CE_SYNC_EXT FALSE
[Use Clock Sequencing]

値: FALSE、TRUE

USE_CLOCK_SEQUENCING FALSE
[CLKOUT<1-7>_SEQUENCE_NUMBER]

値: 1 ~ 7

CLKOUT<1-7>_SEQUENCE_NUMBER 1
  1. 表内のパラメーター値については、Vivado IDE パラメーター値とユーザー パラメーター値の異なるものを示しています。これらの値は、パラメーター名の下に字下げして表記しています。