合成を実行する Tcl コマンドは synth_design です。通常このコマンドは、次の例のように複数のオプションを使用して実行します。
synth_design -part xc7k30tfbg484-2 -top my_topこの例では、synth_design が -part オプションおよび -top オプションを使用して実行されます。
Tcl コンソールから、Tcl コマンド オプションを使用して合成オプションを設定して合成を実行できます。[Tcl Console] ウィンドウで「synth_design -help」と入力すると、オプションのリストを取得できます。次に、-help を使用した例 (synth_design -help) を示します。
Description:
Synthesize a design using Vivado Synthesis and open that design
Syntax:
synth_design [-name <arg>] [-part <arg>] [-constrset <arg>] [-top <arg>]
[-include_dirs <args>] [-generic <args>] [-verilog_define <args>]
[-flatten_hierarchy <arg>] [-gated_clock_conversion <arg>]
[-directive <arg>] [-rtl] [-bufg <arg>] [-no_lc]
[-shreg_min_size <arg>] [-mode <arg>]
[-fsm_extraction <arg>][-rtl_skip_mlo][-rtl_skip_ip]
[-rtl_skip_constraints]
[-keep_equivalent_registers] [-resource_sharing <arg>]
[-cascade_dsp <arg>] [-control_set_opt_threshold <arg>]
[-max_bram <arg>] [-max_uram <arg>]
[-max_dsp <arg>] [-max_bram_cascade_height <arg>]
[-max_uram_cascade_height <arg>] [-retiming] [-no_retimimg]
[-no_srlextract]
[-assert] [-no_timing_driven] [-sfcu] [-debug_log] [-quiet] [-verbose]
Returns:
design object
Usage:
Name Description
------------------------------------------------------------------------------------------------
[-name] Design name
[-part] Target part
[-constrset] Constraint fileset to use.
[-top] Specify the top module name.
[-include_dirs] Specify verilog search directories.
[-generic] Specify generic parameters. Syntax: -generic
<name>=<value> -generic <name>=<value> ...
[-verilog_define] Specify verilog defines. Syntax:
-verilog_define <macro_name>[=<macro_text>]
-verilog_define <macro_name>[=<macro_text>]
[-flatten_hierarchy] Flatten hierarchy during LUT mapping. Values:
zull, none, rebuilt.
Default: rebuilt
[-gated_clock_conversion] Convert clock gating logic to flop enable.
Values: off, on, auto
Default: off
[-directive] Synthesis directive. Values: default,
RuntimeOptimized, AreaOptimized_high,
AreaOptimized_medium, AlternateRoutability,
AreaMapLargeShiftRegToBRAM,
AreaMultThresholdDSP, FewerCarryChains.
Default: default
[-rtl] Elaborate and open an rtl design.
[-bufg] Max number of global clock buffers used by synthesis.
Default = 12
[-no_lc] Disable LUT combining. Do not allow combining.
[-shreg_min_size] Minimum length for chain of registers to be mapped onto
SRL.
Default: 3
[-mode] The design mode. Values: default, out_of_context.
Default: default
[-fsm_extraction] FSM Extraction Encoding. Values: off, one_hot,
sequential, johnson, gray, user_encoding, auto.
Default: auto
[-rtl_skip_mlo] Skip mandatory logic optimization for RTL elaboration of
the design; requires -rtl option.
[-rtl_skip_ip] Exclude subdesign checkpoints in the RTL elaboration of
the design; requires -rtl option.
[-rtl_skip_constraints] Do not load and validate constraints against elaborated
design; requires -rtl option.
[-srl_style] Static SRL Implementation Style. Values: register,
srl, srl_reg, reg_srl, reg_srl_reg.
[-keep_equivalent_registers] Prevents registers sourced by the same logic from being
merged. (Note that the merging can otherwise be
prevented using the synthesis KEEP attribute).[-resource_sharing] Sharing arithmetic operators. Value: auto, on, off.
Default: auto
[-cascade_dsp] Controls how adders summing DSP block outputs will be
implemented. Value: auto, tree, force.
Default: auto
[-control_set_opt_threshold] Threshold for synchronous control set optimization to
lower number of control sets. Valid values are 'auto'
and non-negative integers. The higher the number, the
more control set optimization will be performed and
fewer control sets will result. To disable control set
optimization completely, set to 0.
Default: auto
[-max_bram] Maximum number of block RAM allowed in design. (Note -1
means that the tool will choose the max number allowed
for the part in question).
Default: -1
[-max_uram] Maximum number of UltraRAM blocks allowed in design.
(Note -1 means that the tool will choose the max number
allowed for the part in question).
Default: -1
[-max_dsp] Maximum number of block DSP allowed in design. (Note -1
means that the tool will choose the max number allowed
for the part in question).
Default: -1
[-max_bram_cascade_height] Controls the maximum number of BRAM that can be cascaded
by the tool. (Note -1 means that the tool will choose
the max number allowed for the part in question).
efault: -1
[-max_uram_cascade_height] Controls the maximum number of UtraRAM that can be
cascaded by the tool. (Note -1 means that the tool will
choose the max number allowed for the part in question).
Default: -1
[-retiming] Seeks to improve circuit performance for intra-clock
sequential paths by automatically moving registers
(register balancing) across combinatorial gates or LUTs.
It maintains the original behavior and latency of the
circuit and does not require changes to the RTL sources.
This is for non Versal devices only.
[-no_retimiming] For Versal devices only.Turns off the retiming features
that are on by default in Versal.
[-no_srlextract] Prevents the extraction of shift registers so that they
get implemented as simple registers.
[-assert] Enable VHDL assert statements to be evaluated. A
severity level of failure will stop the synthesis flow
and produce an error.
[-no_timing_driven] Do not run in timing driven mode.
[-sfcu] Run in single-file compilation unit mode.
[-debug_log] Print detailed log files for debugging.
[-quiet] Ignore command errors.
[-verbose] Suspend message limits during command
-generic オプションで VHDL ブール値および std_logic_vector 型を指定する場合、これらはほかの形式には存在しないので特別な処理が必要です。たとえば、TRUE、FALSE、または 0010 の代わりに Verilog 標準を使用する必要があります。
boolean の場合、FALSE の値は次のように指定します。
-generic my_gen=1‘b0
std_logic_vector の場合、0010 の値は次のように指定します。
-generic my_gen=4‘b0010注記: 文字列ジェネリックまたはパラメーターの変更はサポートされていません。
注記: 最上位に
-mode
out_of_context オプションを使用する場合は、RTL に I/O バッファーがインスタンシエートされている場合を除き、PACKAGE_PIN プロパティを使用しないでください。out_of_context オプションを設定すると、トライステート バッファーを含むすべての I/O バッファーが挿入されなくなります。バッファーがない場合、配置でエラーが発生します。コマンドの詳細は、 『Vivado Design Suite Tcl コマンド リファレンス ガイド』 (UG835) を参照してください。Vivado IDE での操作に対応する Tcl コマンドを確認するには、Vivado IDE でコマンドを実行し、[Tcl Console] ウィンドウまたはログ ファイルを参照してください。