VHDL のアーキテクチャ宣言のコード例 - 2023.2 日本語

library IEEE;
use IEEE.std_logic_1164.all;

entity EXAMPLE is
port (
A,B,C : in std_logic;
D,E : out std_logic );
end EXAMPLE;

architecture ARCHI of EXAMPLE is
signal T : std_logic;
begin
...
end ARCHI;