非プロジェクト モードのサンプル スクリプト - 2023.2 日本語

次に、非プロジェクト モードでインプリメンテーションを実行するスクリプト例を示します。スクリプト名が run.tcl である場合、Tcl シェルに「source run.tcl」と入力してスクリプトを呼び出します。

source run.tcl

# Step 1: Read in top-level EDIF netlist from synthesis tool 
read_edif c:/top.edf
# Read in lower level IP core netlists 
read_edif c:/core1.edf
read_edif c:/core2.edf

# Step 2: Specify target device and link the netlists
# Merge lower level cores with top level into single design 
link_design -part xc7k325tfbg900-1 -top top

# Step 3: Read XDC constraints to specify timing requirements 
read_xdc c:/top_timing.xdc
# Read XDC constraints that specify physical constraints such as pin locations 
read_xdc c:/top_physical.xdc

# Step 4: Optimize the design with default settings 
opt_design

# Step 5: Place the design using the default directive and save a checkpoint 
# It is recommended to save progress at certain intermediate steps
# The placed checkpoint can also be routed in multiple runs using different options 
place_design -directive Default
write_checkpoint post_place.dcp

# Step 6: Route the design with the AdvancedSkewModeling directive. For more information
# on router directives type 'route_design -help' in the Vivado Tcl Console route_design -directive AdvancedSkewModeling

# Step 7: Run Timing Summary Report to see timing results report_timing_summary -file post_route_timing.rpt
# Run Utilization Report for device resource utilization 
report_utilization -file post_route_utilization.rpt

# Step 8: Write checkpoint to capture the design database;
# The checkpoint can be used for design analysis in Vivado IDE or TCL API
write_checkpoint post_route.dcp